4.4.2. Global Timer Control Register

Figure 4.6 shows the Global Timer Control Register bit assignments.

Figure 4.6. Global Timer Control Register bit assignments

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Table 4.5 shows the Global Timer Control Register bit assignments.

Table 4.5. Global Timer Control Register bit assignments 

BitsNameFunction
[31:16]-Reserved
[15:8]Prescaler

The prescaler modifies the clock period for the decrementing event for the Counter Register. See Calculating timer intervals for the equation.

[7:4]-Reserved
[3]

Auto-increment[a]

This bit is banked per Cortex-A9 processor.

1’b0: single shot mode.

When the counter reaches the comparator value, sets the event flag. It is the responsibility of software to update the comparator value to get more events.1’b1: auto increment mode.Each time the counter reaches the comparator value, the comparator register is incremented with the auto-increment register, so that more events can be set periodically without any software updates.

[2]IRQ Enable

This bit is banked per Cortex-A9 processor.

If set, the interrupt ID 27 is set as pending in the Interrupt Distributor when the event flag is set in the Timer Status Register.

[1]

Comp Enable[a]

This bit is banked per Cortex-A9 processor.

If set, it enables the comparison between the 64-bit Timer Counter and the related 64-bit Comparator Register.

[0]Timer Enable

Timer enable

1'b0 = Timer is disabled and the counter does not increment.

All registers can still be read and written

1'b1 = Timer is enabled and the counter increments normally.

[a] When the Auto-increment and Comp enable bits are set, an IRQ is generated every auto-increment register value.


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