A.8. Performance monitoring signals

Table A.23 shows the performance monitoring signals. There are as many PMUEVENT buses as there are Cortex-A9 processors in the design.

Table A.23. Performance monitoring signals

NameI/O

Destination

Description
PMUEVENTn[57:0]OPerformance Monitoring Unit (PMU) or External Performance Monitoring Unit

Performance Monitoring Unit event bus for CPUn.

The Cortex-A9 Technical Reference Manual describes the signals and events.

PMUIRQ[N:0]OSystem Integrity Controller or External Performance Monitoring unitInterrupt requests by system metrics, one per Cortex-A9 processor.
PMUSECURE[N:0]OExternal Performance Monitoring unit

Gives the security status of the Cortex-A9 processor:

0 = in Non-secure state

1 = in Secure state.

This signal does not provide input to the CoreSight Trace delivery infrastructure.

PMUPRIV[N:0]O

Gives the status of the Cortex-A9 processor:

0 = in user mode

1 = in privileged mode.

This signal does not provide input to CoreSight.Trace delivery infrastructure.


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