2.2. SCU registers

Table 2.1 shows the SCU registers. Addresses are relative to the base address of the region for the SCU memory map, that is PERIPHBASE[31:13]. All SCU registers are byte accessible and are reset by nSCURESET.

Table 2.1. SCU registers summary

Offset from PERIPHBASE [31:13]

NameSecurity stateReset valueBankedPage
SecureNon- Secure
0x00SCU Control RegisterRW[a]RW

Implementation defined

NoSCU Control Register
0x04SCU Configuration RegisterRORO

Implementation defined

NoSCU Configuration Register
0x08SCU CPU Power Status RegisterRW[a]RW

Implementation defined

NoSCU CPU Power Status Register
0x0CSCU Invalidate All Registers in Secure StateWO[a]-0x00000000NoSCU Invalidate All Registers in Secure State Register
0x40Filtering Start Address RegisterRW[a]RW

Defined by FILTERSTART input

NoFiltering Start Address Register
0x44Filtering End Address RegisterRW[a]RW

Defined by FILTEREND input

NoFiltering End Address Register
0x50SCU Access Control (SAC) RegisterRW[a]RW0x0000000FNoSCU Access Control Register (SAC)
0x54SCU Non-secure Access Control (SNSAC) Register RW[a]RO0x00000000NoSCU Non-secure Access Control Register

[a] This register is writable if the relevant bits in the SAC are set.


SCU registers must not be written with NEON STR instructions.

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