3.3.9. SPI Status Registers

The ICSPISRn characteristics are:

Purpose

Enables a Cortex-A9 processor to access the status of IRQS[N:0] inputs on the distributor.

Usage constraints

There are no usage constraints.

Configurations

Available in all Cortex-A9 MPCore configurations.

Attributes

See the register summary in Table 3.1.

Figure 3.6 shows the ICSPISRn bit assignments.

Figure 3.6. ICSPISRn bit assignments

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Table 3.7 shows the ICSPISRn bit assignments.

Table 3.7. ICSPISRn bit assignments

BitsNameFunction
[31:0]spi_status

Returns the status of the IRQS[N:0] inputs on the distributor:

Bit [X] = 0

IRQS[X] is LOW

Bit [X] = 1

IRQS[X] is HIGH.

Note

The IRQS that X refers to depends on its bit position and the base address offset of the spi_status Register as Figure 3.7 shows.

These bits return the actual status of the IRQS signals. The pending_set and pending_clr Registers can also provide the IRQS status but because you can write to these registers then they might not contain the actual status of the IRQS signals.


Figure 3.7 shows the address map that the distributor provides for the SPIs.

Figure 3.7. ICSPISRn address map

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In Figure 3.7 the values for the SPIs are read-only. This register contains the values for the SPIs for the corresponding Cortex-A9 processor interface. The distributor provides up to 7 registers. If you configure the Interrupt Controller to use fewer than 224 SPIs then it reduces the number of registers accordingly. For locations where interrupts are not implemented then the distributor:

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