A.10. Parity error signals

Table A.25 shows parity error reporting signals. These signals are present only if parity is defined. The number of sets of PARITYFAIL signals corresponds to the number of Cortex-A9 processors present in the design.

Table A.25. Error reporting signals

NameI/O

Destination

Description
PARITYFAILn[7:0]OSystem integrity controller

Parity output pin from the RAM array for Cortex-A9 processor n.

Indicates a parity fail.

0 no parity fail

1 parity fail

Bit [7] BTAC parity error

Bit [6] GHB parity error

Bit [5] Instruction tag RAM parity error

Bit [4] Instruction data RAM parity error

Bit [3] Main TLB parity error

Bit [2] D outer RAM parity error

Bit [1] Data tag RAM parity error

Bit [0] Data data RAM parity error.

PARITYFAILSCU[N:0]OParity output pin from the SCU tag RAMs. ORed output from each Cortex-A9 processor present in the design.

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