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Table A.9 shows power control interface signals.
Table A.9. Power control interface signals
Name | I/O | Source or Destination | Description |
---|---|---|---|
CPUCLAMP[N:0] | I | Power controller | Interrupt interface clamps control signals: CPUCLAMP[3] CPU3 interface CPUCLAMP[2] CPU2 interface CPUCLAMP[1] CPU1 interface CPUCLAMP[0] CPU0 interface. |
CPURAMCLAMP[N:0] | I | Enables the clamp cells in Dormant mode. | |
SCURAMCLAMP | I | Enables the SCU clamp cells in Dormant mode. | |
NEONCLAMP[N:0][a] | I | Activates the Cortex-A9 MPE SIMD logic clamps:0 = clamps not active1 = clamps active. | |
PWRCTLI0[1:0] | I | Reset value for CPU0 status field, bits [1:0], of SCU CPU Power Status Register[1:0]. | |
PWRCTLI1[1:0] | I | Reset value for CPU0 status field, bits [9:8], of SCU CPU Power Status Register. [9:8]. | |
PWRCTLI2[1:0] | I | Reset value for CPU0 status field, bits [17:16], of SCU CPU Power Status Register. [17:16]. | |
PWRCTLI3[1:0] | I | Reset value for CPU0 status field, bits [25:24], of SCU CPU Power Status Register. [25:24]. | |
PWRCTLO0[1:0] | O | b0x CPU0 must be powered on b10 CPU0 can enter dormant mode b11 CPU0 can enter powered-off mode. | |
PWRCTLO1[1:0] | O | b0x CPU1 must be powered on b10 CPU1 can enter dormant mode b11 CPU1 can enter powered-off mode. This signal exists only if CPU1 is present. | |
PWRCTLO2[1:0] | O | Power controller | b0x CPU2 must be powered on b10 CPU2 can enter dormant mode b11 CPU2 can enter powered-off mode. This signal exists only if CPU2 is present. |
PWRCTLO3[1:0] | O | b0x CPU3 must be powered on b10 CPU3 can enter dormant mode b11 CPU3 can enter powered-off mode This signal exists only if CPU3 is present. | |
SCUIDLE | O | L2C-310 or power controller | In the case of the L2C-310, the SCUIDLE output of the Cortex-A9 MPCore can be connected to the STOPCLK input of the L2C-310. |
[a] Only if an MPE is present |
See SCU CPU Power Status Register. See also Communication to the Power Management Controller.