Cortex-A9 MPCore Technical Reference Manual: A.7. AXI interfaces

Cortex-A9 MPCore Technical Reference Manual

Revision: r3p0

Home > Signal Descriptions > AXI interfaces

A.7. AXI interfaces

In Cortex-A9 designs there can be two AXI master ports and an Accelerator Coherence Port, an AXI slave. The following sections describe the AXI interfaces:

AXI Master0 signals
AXI Master1 signals
AXI ACP signals.

Copyright © 2008-2011 ARM. All rights reserved.	ARM DDI 0407G
Non-Confidential	ID072711
PDF version

Home > Signal Descriptions > AXI interfaces