5.2.5. Individual processor power-on SIMD MPE reset

This reset initializes all the SIMD logic of the MPE in a single Cortex-A9 processor.

It is expected to be applied when the SIMD part of the MPE exits from powerdown state.

This reset only applies to configurations where SIMD MPE logic is implemented in its own dedicated power domain, separated from the rest of the processor logic.

ARM recommends the following reset sequence on power-on for an individual CPU SIMD MPE power-on:

  1. Apply nNEONRESET[n].

  2. Wait for at least nine CLK cycles. There is no harm in applying more clock cycles than this, and maximum redundancy can be achieved by for example applying 15 cycles on every clock domain.

  3. Assert NEONCLKOFF[n] with a value of 1’b1.

  4. Wait for the equivalent of approximately 10 cycles, depending on your implementation. This compensates for clock and reset tree latencies.

  5. Release nNEONRESET[n].

  6. Wait for the equivalent of approximately another 10 cycles, again to compensate for clock and reset tree latencies.

  7. Deassert NEONCLKOFF[n]. This ensures that all registers in the SIMD MPE part of the processor see the same CLK edge on exit from the reset sequence.

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