5.2.3. Individual processor power-on reset

This reset initializes the whole logic in a single Cortex-A9 processor, including its debug logic. It is expected to be applied when this individual Cortex-A9 processor exits from power down or dormant state.

This reset only applies to configurations where each individual Cortex-A9 processor is implemented in its own power domain.

The sequence is as follows:

  1. Apply nCPURESET[n] and nDBGRESET[n], plus nNEONRESET[n] if the SIMD MPE is present. nWDRESET[n] reset can also be applied optionally if you want to reset the corresponding Watchdog flag.

  2. Wait for at least nine CLK cycles, plus at least one cycle in each other clock domain, or more if the documentation for other components requests it. There is no harm in applying more clock cycles than this, and maximum redundancy can be achieved by for example applying 15 cycles on every clock domain.

  3. Assert CPUCLKOFF[n] with a value of 1’b1 and, if there is a SIMD MPE present, NEONCLKOFF[n].

  4. Wait for the equivalent of approximately 10 cycles, depending on your implementation. This compensates for clock and reset tree latencies.

  5. Release all resets.

  6. Wait for the equivalent of another approximately 10 cycles, again to compensate for clock and reset tree latencies.

  7. Deassert CPUCLKOFF[n] and NEONCLKOFF[n]. This ensures that all registers in the processor, and in the SIMD MPE, see the same CLK edge on exit from the reset sequence.

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