4.2.3. Private Timer Control Register

Figure 4.1 shows the Private Timer Control Register bit assignments.

Figure 4.1. Private Timer Control Register bit assignments

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Table 4.2 shows the Private Timer Control Register bit assignments.

Table 4.2. Private Timer Control Register bit assignments 

BitsNameFunction
[31:16]-UNK/SBZP.
[15:8]Prescaler

The prescaler modifies the clock period for the decrementing event for the Counter Register. See Calculating timer intervals for the equation.

[7:3]-UNK/SBZP.
[2]IRQ Enable

If set, the interrupt ID 29 is set as pending in the Interrupt Distributor when the event flag is set in the Timer Status Register.

[1]Auto reload

1'b0 = Single shot mode.Counter decrements down to zero, sets the event flag and stops.1'b1 = Auto-reload mode.Each time the Counter Register reaches zero, it is reloaded with the value contained in the Timer Load Register.

[0]Timer Enable

Timer enable

1'b0 = Timer is disabled and the counter does not decrement.

All registers can still be read and written

1'b1 = Timer is enabled and the counter decrements normally.


The timer is incremented every prescaler value+1. For example, if the prescaler has a value of five then the global timer is incremented every six clock cycles. PERIPHCLK is the reference clock for this.

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