4.2.9. Watchdog Reset Status Register

Figure 4.5 shows the Watchdog Reset Status Register bit assignment.

Figure 4.5. Watchdog Reset Status Register bit assignment

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The reset flag is a sticky bit that is automatically set, in watchdog mode, when the Counter Register reaches zero and a reset request is sent accordingly.

The reset flag is cleared when written with a value of 1. Trying to write a zero to the reset flag or a one when it is not set has no effect. This flag is not reset by normal Cortex-A9 processor resets but has its own reset line, nWDRESET. nWDRESET must not be asserted when the Cortex-A9 processor reset assertion is the result of a watchdog reset request with WDRESETREQ. This distinction enables software to differentiate between a normal boot sequence, reset flag is zero, and one caused by a previous watchdog time-out, reset flag set to one.

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