3.1.1. Interrupt Controller Clock frequency

The clock period is configured, during integration, as a multiple of the MPCore clock period. This multiple, N, must be greater than or equal to two. As a consequence, the minimum pulse width of signals driving external interrupt lines is N Cortex-A9 processor clock cycles. See Chapter 5 Clocks, Resets, and Power Management for a description of PERIPHCLK and PERIPHCLKEN.

The timers and watchdogs use the same clock as the interrupt controller.

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