Cortex™-A9 MPCore® Technical Reference Manual

Revision: r3p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the Cortex-A9 MPCore processor
1.2. Compliance
1.2.1. ARM architecture
1.2.2. Advanced Microcontroller Bus Architecture
1.2.3. Program Flow Trace architecture
1.2.4. Debug architecture
1.2.5. Generic Interrupt Controller architecture
1.3. Configurable options
1.4. Test features
1.5. Private Memory Region
1.6. Interfaces
1.6.1. AMBA AXI interfaces
1.6.2. Interrupts interface
1.6.3. Debug interfaces
1.6.4. Design for Test interface
1.7. MPCore considerations
1.7.1. About Cortex-A9 MPCore coherency
1.7.2. Registers with multiprocessor uses
1.7.3. Maintenance operations broadcasting
1.8. Product documentation and design flow
1.8.1. Documentation
1.8.2. Design flow
1.9. Product revisions
1.9.1. Differences in functionality between r0p0 and r0p1
1.9.2. Differences in functionality between r0p1 and r1p0
1.9.3. Differences in functionality between r1p0 and r2p0
1.9.4. Differences in functionality between r2p0 and r2p1
1.9.5. Differences in functionality between r2p1 and r2p2
1.9.6. Differences in functionality between r2p2 and r3p0
2. Snoop Control Unit
2.1. About the SCU
2.1.1. TrustZone extensions
2.1.2. SCU event monitoring
2.2. SCU registers
2.2.1. SCU Control Register
2.2.2. SCU Configuration Register
2.2.3. SCU CPU Power Status Register
2.2.4. SCU Invalidate All Registers in Secure State Register
2.2.5. Filtering Start Address Register
2.2.6. Filtering End Address Register
2.2.7. SCU Access Control Register (SAC)
2.2.8. SCU Non-secure Access Control Register
2.3. AMBA AXI Master Port Interfaces
2.3.1. AXI issuing capabilities
2.3.2. Cortex-A9 MPCore AXI transactions
2.3.3. AXI transaction IDs
2.3.4. AXI USER attributes encodings
2.3.5. Address filtering capabilities
2.3.6. Device accesses filtering
2.3.7. AXI master interface clocking
2.4. Accelerator Coherency Port
2.4.1. ACP requests
2.4.2. ACP interface clocking
2.4.3. ACP limitations
2.5. Event communication with an external agent using WFE/SEV
3. Interrupt Controller
3.1. About the Interrupt Controller
3.1.1. Interrupt Controller Clock frequency
3.1.2. Interrupt Distributor interrupt sources
3.1.3. Interrupt Distributor arbitration
3.1.4. Cortex-A9 MPCore 1-N interrupt model handling
3.2. Security extensions support
3.2.1. Priority formats
3.2.2. Using CFGSDISABLE
3.3. Distributor register descriptions
3.3.1. Distributor Control Register
3.3.2. Interrupt Controller Type Register
3.3.3. Distributor Implementer Identification Register
3.3.4. Interrupt Set-Enable Registers
3.3.5. Interrupt Clear-Enable Registers
3.3.6. Interrupt Processor Targets Registers
3.3.7. Interrupt Configuration Registers
3.3.8. PPI Status Register
3.3.9. SPI Status Registers
3.4. Interrupt interface register descriptions
3.4.1. CPU Interface Implementer Identification Register
4. Global timer, private timers, and watchdog registers
4.1. About the private timer and watchdog blocks
4.1.1. Calculating timer intervals
4.1.2. Security extensions
4.2. Private timer and watchdog registers
4.2.1. Private Timer Load Register
4.2.2. Private Timer Counter Register
4.2.3. Private Timer Control Register
4.2.4. Private Timer Interrupt Status Register
4.2.5. Watchdog Load Register
4.2.6. Watchdog Counter Register
4.2.7. Watchdog Control Register
4.2.8. Watchdog Interrupt Status Register
4.2.9. Watchdog Reset Status Register
4.2.10. Watchdog Disable Register
4.3. About the Global Timer
4.4. Global timer registers
4.4.1. Global Timer Counter Registers, 0x00 and 0x04
4.4.2. Global Timer Control Register
4.4.3. Global Timer Interrupt Status Register
4.4.4. Comparator Value Registers, 0x10 and 0x14
4.4.5. Auto-increment Register, 0x18
5. Clocks, Resets, and Power Management
5.1. Clocks
5.2. Resets
5.2.1. Cortex-A9 MPCore power-on reset
5.2.2. Cortex-A9 MPCore software reset
5.2.3. Individual processor power-on reset
5.2.4. Individual processor software reset
5.2.5. Individual processor power-on SIMD MPE reset
5.2.6. Cortex-A9 MPCore debug reset
5.2.7. Individual processor debug reset
5.2.8. Individual processor watchdog flag reset
5.3. Power management
5.3.1. Individual Cortex-A9 processor power management
5.3.2. Communication to the Power Management Controller
5.3.3. Cortex-A9 MPCore power domains
5.3.4. Multiprocessor bring-up
6. Debug
6.1. External Debug Interface Signals
6.2. Cortex-A9 MPCore APB Debug interface and memory map
6.2.1. A single Cortex-A9 processor configuration
6.2.2. Two Cortex-A9 processors configuration
6.2.3. Three Cortex-A9 processors configuration
6.2.4. Four Cortex-A9 processors configuration
A. Signal Descriptions
A.1. Clock and clock control signals
A.2. Resets and reset control signals
A.3. Interrupts
A.4. Configuration signals
A.5. WFE and WFI Standby signals
A.6. Power management signals
A.7. AXI interfaces
A.7.1. AXI Master0 signals
A.7.2. AXI Master1 signals
A.7.3. AXI ACP signals
A.8. Performance monitoring signals
A.9. Exception flags signals
A.10. Parity error signals
A.11. MBIST interface
A.12. Scan test signal
A.13. External Debug interface
A.13.1. Authentication interface
A.13.2. APB interface signals
A.13.3. Cross trigger interface signals
A.13.4. Miscellaneous debug interface signals
A.14. PTM interface signals
B. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. Example multiprocessor configuration
2.1. SCU Control Register bit assignments
2.2. SCU Configuration Register bit assignments
2.3. SCU CPU Power Status Register bit assignments
2.4. SCU Invalidate All Registers in Secure state bit assignments
2.5. Filtering Start Address Register bit assignments
2.6. Filtering End Address Register bit assignments
2.7. SAC register bit assignments
2.8. SNSAC register bit assignments
2.9. Timing diagram for INCLKEN with three-to-two clock ratio between CPU and AXI Slave CLK
2.10. Timing diagram for INCLKEN with five-to-two clock ratio between CPU and AXI Slave CLK
2.11. Timing diagram for OUTCLKEN with three-to-two clock ratio between CPU and AXI Slave CLK
2.12. Timing diagram for OUTCLKEN with five-to-two clock ratio between CPU and AXI Slave CLK
2.13. ACLKENS timing example
3.1. ICDDCR bit assignments for Secure accesses
3.2. ICDDCR bit assignments for Non-secure accesses
3.3. ICDICTR bit assignments
3.4. ICDIIDR bit assignments
3.5. ICPPISR bit assignments
3.6. ICSPISRn bit assignments
3.7. ICSPISRn address map
3.8. ICCIIDR bit assignments
4.1. Private Timer Control Register bit assignments
4.2. Private Timer Interrupt Status Register bit assignment
4.3. Watchdog Control Register bit assignments
4.4. Watchdog Interrupt Status Register bit assignment
4.5. Watchdog Reset Status Register bit assignment
4.6. Global Timer Control Register bit assignments
4.7. Global Timer Interrupt Status Register bit assignment
5.1. Three-to-one timing ratio
5.2. Cortex-A9 MPCore power domains and clamps
6.1. External debug interface signals in CortexA9 MPCore designs

List of Tables

1.1. Configurable options for the Cortex-A9 MPCore processor
1.2. Permitted access sizes for private memory regions
1.3. Cortex-A9 MPCore private memory region
2.1. SCU registers summary
2.2. SCU Control Register bit assignments
2.3. SCU Configuration Register bit assignments
2.4. SCU CPU Power Status Register bit assignments
2.5. SCU Invalidate All Registers in Secure state bit assignments
2.6. Filtering Start Address Register bit assignments
2.7. Filtering End Address Register bit assignments
2.8. SAC register bit assignments
2.9. SNSAC register bit assignments
2.10. AXI master interface attributes
2.11. ARID encodings
2.12. AWIDMx encodings
2.13. ARUSERMx[6:0] encodings
2.14. AWUSERMx[8:0] encodings
3.1. Distributor register summary
3.2. ICDDCR bit assignments for secure accesses
3.3. ICDDCR bit assignments for Non-secure accesses
3.4. ICDICTR bit assignments
3.5. ICDIIDR bit assignments
3.6. ICPPISR bit assignments
3.7. ICSPISRn bit assignments
3.8. Cortex-A9 processor interface register summary
3.9. ICCIIDR bit assignments
4.1. Timer and watchdog registers 
4.2. Private Timer Control Register bit assignments 
4.3. Watchdog Control Register bit assignments 
4.4. Global timer registers
4.5. Global Timer Control Register bit assignments 
5.1. Reset combinations in a Cortex-A9 MPCore system
5.2. Cortex-A9 MPCore power modes
A.1. Cortex-A9 MPCore clocks and clock control signals
A.2. Reset signals
A.3. Reset clock control signals
A.4. Watchdog request reset signal
A.5. Interrupt line signals
A.6. Configuration signals
A.7. Security control signals
A.8. Standby and wait for event signals
A.9. Power control interface signals
A.10. Write address signals for AXI Master0
A.11. Write data signals for AXI Master0
A.12. Write response signals for AXI Master0
A.13. Read address signals for AXI Master0
A.14. L2C-310 signals on M0
A.15. Read data signals for AXI Master0
A.16. AXI Master0 clock enable signals
A.17. Write address signals for AXI ACP
A.18. Write data signals for AXI ACP
A.19. Write response signals for AXI ACP
A.20. Read address signals for AXI ACP
A.21. Read data signals for AXI ACP
A.22. ACLKENS signal
A.23. Performance monitoring signals
A.24. Exception flags signals
A.25. Error reporting signals
A.26. MBIST interface signals
A.27. MBIST signals with parity support implemented
A.28. MBIST signals without parity support implemented
A.29. Scan test signal
A.30. Authentication interface signals
A.31. APB interface signals
A.32. Cross trigger interface signals
A.33. Miscellaneous debug signals
A.34. PTM interface signals
B.1. Issue A
B.2. Differences between issue A and issue B
B.3. Differences between issue B and issue C
B.4. Differences between issue C and issue D
B.5. Differences between D and F
B.6. Differences between issue F and issue G

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Confidentiality Status

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A04 April 2008First release for r0p0
Revision B08 July 2008First release for r0p1
Revision C16 December 2008First release for r1p0
Revision D2 October 2009First release for r2p0
Revision E27 November 2009Second release for r2p0
Revision F30 April 2010First release for r2p2
Revision G19 July 2011First release for r3p0
Copyright © 2008-2011 ARM. All rights reserved.ARM DDI 0407G
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