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| Non-Confidential | ID032812 |
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The Cortex-A9 MPCore Bus Interface Unit supports the following AXI bus ratios relative to CLK:
Integer ratios through clock enable: 1:1, 2:1, 3:1, …
Half-integer ratios through clock enable: 1.5, 2.5 and 3.5 ratios.
In all cases AXI transfers remain synchronous. There is no requirement for an asynchronous AXI interface with integer and half integer ratios. The ratios are configured through external pins, with the following signals that qualify the input and output signals on AXI:
INCLKENM0 and OUTCLKENM0
INCLKENM1 and OUTCLKENM1.
Figure 2.9 shows a timing diagram example of read data return from an AXI slave back into the Cortex-A9 MPCore processor, with a three-to-two clock timing ratio.
Figure 2.10 shows a timing diagram example of read data return from an AXI slave back into the Cortex-A9 MPCore processor, with a five-to-two clock timing ratio.
Figure 2.11 shows a timing diagram example of data write from the Cortex-A9 MPCore processor into an AXI slave, with a three-to-two clock timing ratio.
Figure 2.11. Timing diagram for OUTCLKEN with three-to-two clock ratio between CPU and AXI Slave CLK
Figure 2.12 shows a timing diagram example of data write from the Cortex-A9 MPCore processor into an AXI slave, with a five-to-two clock timing ratio.
| Copyright © 2008-2012 ARM. All rights reserved. | ARM DDI 0407H |
| Non-Confidential | ID032812 |
| PDF version | |
| Home > Snoop Control Unit > AMBA AXI Master Port Interfaces > AXI master interface clocking |