6.2. Cortex-A9 MPCore APB Debug interface
and memory map
Each Cortex-A9 processor contains two 4KB CoreSight components,
for the debug and performance monitor resources, mapped in a contiguous
8KB memory region.See the Cortex-A9 TRM for detailed memory mapping
of this 8KB memory region.
The Cortex-A9 MPCore has a single Debug APB interface to access
the individual Cortex-A9 processors in the cluster.Because it contains
between one and four individual Cortex-A9 processors, the Cortex-A9
MPCore appears as an 8KB, 16KB, 24KB, or 32KB CoreSight memory region,
accessed when PSELDBG is asserted.
The following sections describe the uses of PADDRDBG in
the following Cortex-A9 MPCore configurations:
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