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The ICDICTR characteristics are:
Provides information about the configuration of the Interrupt Controller.
There are no usage constraints.
Available in all Cortex-A9 MPCore configurations.
See the register summary in Table 3.1.
Figure 3.3 shows the ICDICTR bit assignments.
Table 3.4 shows the ICDICTR bit assignments.
Table 3.4. ICDICTR bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:16] | - | Reserved |
| [15:11] | LSPI | Returns the number of Lockable Shared Peripheral Interrupts (LSPIs) that the controller contains. The encoding is:
When CFGSDISABLE is HIGH, the interrupt controller prevents writes to any register location that controls the operating state of an LSPI. |
| [10] | SecurityExtn | Returns the number of security domains that the controller contains:
This bit always returns the value one. |
| [9:8] | - | Reserved |
| [7:5] | CPU number | The encoding is:
|
| [4:0] | IT lines number | The encoding is:
All other values not used. |
[a] The distributor always uses interrupts of IDs 0 to 31 to control any SGIs and PPIs that the Interrupt Controller might contain. | ||