| Copyright © 2008-2012 ARM. All rights reserved. | ARM DDI 0407H |
| Non-Confidential | ID032812 |
 PDF version | |
| Home > Global timer, private timers, and watchdog registers > About the Global Timer |
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The global timer has the following features:
The global timer is a 64-bit incrementing counter with an auto-incrementing feature. It continues incrementing after sending interrupts.
The global timer is memory mapped in the private memory region. See Private Memory Region.
The global timer is accessed at reset in Secure State only. See SCU Non-secure Access Control Register.
The global timer is accessible to all Cortex-A9 processors in the cluster. Each Cortex-A9 processor has a private 64-bit comparator that is used to assert a private interrupt when the global timer has reached the comparator value. All the Cortex-A9 processors in a design use the banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt Controller as a Private Peripheral Interrupt. See Interrupt Distributor interrupt sources.
The global timer is clocked by PERIPHCLK.
From r2p0 the comparators for each processor with the global timer fire when the timer value is greater than or equal to. In previous revisions the comparators fired when the timer value was equal to.
The global timer does not stop counting when any of the processors are in debug state.
| Copyright © 2008-2012 ARM. All rights reserved. | ARM DDI 0407H |
| Non-Confidential | ID032812 |
| PDF version | |
| Home > Global timer, private timers, and watchdog registers > About the Global Timer |