2.3.1. AXI issuing capabilities

The Cortex-A9 MPCore L2 interface can have two 64-bit wide AXI bus masters. In a two bus master configuration there is also an option to configure address filtering. See Address filtering capabilities. Table 2.10 shows the AXI master interface attributes.

Table 2.10. AXI master interface attributes

Write Issuing Capability

10 per processor, including:

  • 8 non-cacheable writes

  • 2 evictions.

2 additional writes can also be performed for eviction traffic from the SCU.

3 more write transactions can be issued if the ACP is implemented.

Read Issuing Capability

14 per processor, including:

  • 4 instruction reads

  • 6 linefill reads.

  • 4 non-cacheable read.

7 more read transactions can be issued if the ACP is implemented.

Combined Issuing Capability

Up to 24 per processor.

Plus 2 for SCU evictions

10 more transactions can be issued, if the ACP is implemented.

Write ID Capability


Write Interleave Capability1
Write ID Width


Read ID Capability


Read ID Width


The AXI protocol and meaning of each AXI signal are not described in this document. For more information see AMBA AXI Protocol v1.0 Specification.


These numbers are the theoretical maximums for the Cortex-A9 MP processor. A typical system is unlikely to reach these numbers. ARM recommends that you perform profiling to tailor your system resources appropriately for optimum performance.

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