2.3.1. Definitions of throughput and latency

The definitions of throughput and latency are:

Throughput

Throughput is the number of cycles after issue that another instruction can begin execution.

Latency

Latency is the number of cycles after which the data is available for another operation. The forward latency, Fwd, is relevant for Read After Write (RAW) hazards. The writeback latency, Wbck, is relevant for Write-After-Write (WAW) hazards. See Table 2.1.

Latency values assume that the instruction has been issued and that neither the FPU pipeline nor the Cortex-A9 pipeline is stalled.

Table 2.1 shows:

Table 2.1. FPU instruction throughput and latency cycles

Old ARM assembler mnemonicUALSingle Precision Double Precision
ThroughputLatencyThroughputLatency
 FwdWbck FwdWbck

FADD

FSUB

FCVT

FSHTOD, FSHTOS

FSITOD, FSITOS

FTOSHD, FTOSHS

FTOSID, FTOSIS

FTOSL, FTOUH

FTOUI{Z}D, FTOUI{Z}S

FTOULD, FTOULS, FUHTOD, FUHTOS

FUITOD, FUITOS

FULTOD, FULTOS

VADD

VSUB

VCVT

1414

FMUL

FNMUL

VMUL

VNMUL

1526

FMAC

FNMAC

FMSC

FNMSC

VMLA

VMLS

VNMLS

VNMLA

1829

FCPY

FABS

FNEG

FCONST

VMOV

VABS

VNEG

VMOV

112112

FMRS[a]

FMRR(S/D)

FMRD(L/H

VMOV1-01-0

FMSR[b]

FM(S/D)RR

FMD(L/H)R

VMOV112112
FMSTATVMRS1-01-0
FDIV

VDIV

10152025
FSQRT

VSQRT

13172832

FCMP

FCMPE

FCMPZ

FCMPEZ

VCMP

VCMP{E}

VCMP{E}

VCMP{E}

114114
-

FCVT(T/B)

.F16.F32

122---
-

FCVT(T/B)

.F32.F16

1-4---

[a] FPU to ARM.

[b] ARM to FPU.


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