Cortex-A9 Floating-Point Unit Technical Reference Manual: Appendix A. Revisions

Appendix A. Revisions

This appendix describes the technical changes between released issues of this book.

Table A.1. Issue A

Change	Location
First release	-

Table A.2. Differences between Issue A and Issue B

Change	Location
UAL instructions to access registers are added to register descriptions	Register descriptions

Table A.3. Differences between issue B and issue C

Change	Location
The mnemonic for the `FMXR` instruction is changed to `VMSR`	To use the FPU in Secure state only and To use the FPU in Secure state and Non-secure state
Updated FPSCR bit assignments table	Table 2.5

Table A.4. Differences between issue C and issue D

Table A.5. Differences between issue D and Issue E

Change	Location
No technical change	-

Table A.6. Differences between issue E and Issue F

Change	Location
Harmonized FPEXC bit descriptions with the MPE TRM descriptions	Table 2.6

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