| Copyright © 2008-2010 ARM. All rights reserved. | ARM DDI 0408F |
| Non-Confidential | ID050110 |
 PDF version | |
| Home > Programmers Model > Instruction throughput and latency > Definitions of throughput and latency |
| |||
| Home > Programmers Model > Instruction throughput and latency > Definitions of throughput and latency | |||
The definitions of throughput and latency are:
Throughput is the number of cycles after issue that another instruction can begin execution.
Latency is the number of cycles after which the data is available for another operation. The forward latency, Fwd, is relevant for Read After Write (RAW) hazards. The writeback latency, Wbck, is relevant for Write-After-Write (WAW) hazards. See Table 2.1.
Latency values assume that the instruction has been issued and that neither the FPU pipeline nor the Cortex-A9 pipeline is stalled.
Table 2.1 shows:
the FPU instruction throughput and latency cycles for all operations except loads, stores and system register accesses
the old ARM assembler mnemonics and the ARM Unified Assembler Language (UAL) mnemonics.
Table 2.1. FPU instruction throughput and latency cycles
| Old ARM assembler mnemonic | UAL | Single Precision | Double Precision | ||||
|---|---|---|---|---|---|---|---|
| Throughput | Latency | Throughput | Latency | ||||
| Fwd | Wbck | Fwd | Wbck | ||||
|
| 1 | 4 | 1 | 4 | ||
|
| 1 | 5 | 2 | 6 | ||
|
| 1 | 8 | 2 | 9 | ||
|
| 1 | 1 | 2 | 1 | 1 | 2 |
| VMOV | 1 | - | 0 | 1 | - | 0 |
| VMOV | 1 | 1 | 2 | 1 | 1 | 2 |
FMSTAT | VMRS | 1 | - | 0 | 1 | - | 0 |
FDIV |
| 10 | 15 | 20 | 25 | ||
FSQRT |
| 13 | 17 | 28 | 32 | ||
|
| 1 | 1 | 4 | 1 | 1 | 4 |
| - |
| 1 | 2 | 2 | - | - | - |
| - |
| 1 | - | 4 | - | - | - |
[a] FPU to ARM. [b] ARM to FPU. | |||||||
| Copyright © 2008-2010 ARM. All rights reserved. | ARM DDI 0408F |
| Non-Confidential | ID050110 |
| PDF version | |
| Home > Programmers Model > Instruction throughput and latency > Definitions of throughput and latency |