Cortex-A9 Floating-Point Unit Technical Reference Manual: 2.3.2. Instruction throughput and latency

the FPU instruction throughput and latency cycles for all operations except loads, stores and system register accesses
the old ARM assembler mnemonics and the ARM Unified Assembler Language (UAL) mnemonics.

Table 2.1. FPU instruction throughput and latency cycles

Old ARM assembler mnemonic	UAL	Single Precision			Double Precision
		Throughput	Latency		Throughput	Latency
			Fwd	Wbck		Fwd	Wbck
`FADD` `FSUB` `FCVT` `FSHTOD`, `FSHTOS` `FSITOD`, `FSITOS` `FTOSHD`, `FTOSHS` `FTOSID`, `FTOSIS` `FTOSL`, `FTOUH` `FTOUI{Z}D`, `FTOUI{Z}S` `FTOULD`, `FTOULS`, `FUHTOD`, `FUHTOS` `FUITOD`, `FUITOS` `FULTOD`, `FULTOS`	`VADD` `VSUB` `VCVT`	1	4		1	4
`FMUL` `FNMUL`	`VMUL` `VNMUL`	1	5		2	6
`FMAC` `FNMAC` `FMSC` `FNMSC`	`VMLA` `VMLS` `VNMLS` `VNMLA`	1	8		2	9
`FCPY` `FABS` `FNEG` `FCONST`	`VMOV` `VABS` `VNEG` `VMOV`	1	1	2	1	1	2
`FMRS` `FMRR(S/D)` `FMRD(L/H`)	`VMOV`^[a]	1	-	3^[b]	1	-	3^[b]
`FMSR` `FM(S/D)RR` `FMD(L/H)R`	`VMOV`^[c]	1	1	2	1	1	2
`FMSTAT`	`VMRS`	1	-	3^[b]	1	-	3^[b]
`FDIV`	`VDIV`	10	15		20	25
`FSQRT`	`VSQRT`	13	17		28	32
`FCMP` `FCMPE` `FCMPZ` `FCMPEZ`	`VCMP` `VCMP{E}` `VCMP{E}` `VCMP{E}`	1	1	4	1	1	4
-	`FCVT(T/B)` `.F16.F32`	1	2	2	-	-	-
-	`FCVT(T/B)` `.F32.F16`	1	-	4	-	-	-
^[a]FPU to ARM. ^[b]The writeback number for these instructions is given from an ARM core writeback point of view. It reflects the penalty of moving data from the FPU into the ARM core register file before the following ARM instruction can use the moved data. ^[c]ARM to FPU.

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