Appendix A. Revisions

This appendix describes the technical changes between released issues of this book.

Table A.1. Issue A

First release-

Table A.2. Differences between Issue A and Issue B

UAL instructions to access registers are added to register descriptionsRegister descriptions

Table A.3. Differences between issue B and issue C

The mnemonic for the FMXR instruction is changed to VMSRTo use the FPU in Secure state only and To use the FPU in Secure state and Non-secure state
Updated FPSCR bit assignments tableTable 2.5

Table A.4. Differences between issue C and issue D

Front matter Preface
Revision number updatesTable 2.2 and Table 2.4
SBZ replaced with UNK/SBZPFig 2-3 and Table 2-6, Fig 2-5 and Table 3-8

Table A.5. Differences between issue D and Issue E

No technical change-

Table A.6. Differences between issue E and Issue F

Harmonized FPEXC bit descriptions with the MPE TRM descriptionsTable 2.6

Table A.7. Differences between issue F and issue G

Updated latency information for VMOV and VMRS instructionsTable 2.1All versions
Updated information about reset values for the MVFR1 and MVFR0 registersRegister summaryAll versions
Updated revision numberTable 2.2r3p0
Table 2.4r3p0

Table A.8. Differences between issue G and Issue H

Updated revision numberTable 2.2r4p0
Table 2.4

Table A.9. Differences between issue H and Issue I

No technical change-

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