2.4. Register summary

Table 2.2 shows the FPU system registers. All FPU system registers are 32-bit wide. Reserved register addresses are RAZ/WI.

Table 2.2. FPU system registers

NameTypeResetDescription
FPSID RO 0x41033094See Floating-Point System ID Register
FPSCRRW0x00000000See Floating-Point Status and Control Register
MVFR1RO 0x01000011[a]See the ARM Architecture Reference Manual
MVFR0RO 0x10110221[a]Seethe ARM Architecture Reference Manual
FPEXCRW 0x00000000See Floating-Point Exception Register

[a] The reset values in this document are valid for an FPU-only configuration of the Cortex-A9.

In Cortex-A9 configurations with the Media Processing Engine, SIMD Extensions, the MVFR0 and MVFR1 values are different. See the Cortex-A9 NEON Media Processing Engine Technical Reference Manual for more information.


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