2.5.2. Floating-Point Status and Control Register

The FPSCR characteristics are:

Purpose

Provides User-level control of the FPU.

Usage constraints

There are no usage constraints.

Configurations

Available in all FPU configurations.

Attributes

See the register summary in Table 2.2.

Figure 2.2 shows the FPSCR bit assignments.

Figure 2.2. FPSCR bit assignments

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Table 2.5 shows the FPSCR bit assignments.

Table 2.5. FPSCR bit assignments

Bits Name Function
[31] N Set to 1 if a comparison operation produces a less than result.
[30]Z Set to 1 if a comparison operation produces an equal result.
[29] C Set to 1 if a comparison operation produces an equal, greater than, or unordered result.
[28] V Set to 1 if a comparison operation produces an unordered result.
[27] -UNK/SBZP.
[26] AHP

Alternative Half-Precision control bit:

0

IEEE half-precision format selected.

1

Alternative half-precision.

[25] DN

Default NaN mode control bit:

0

NaN operands propagate through to the output of a floating-point operation.

1

Any operation involving one or more NaNs returns the Default NaN.

Advanced SIMD arithmetic always uses the Default NaN setting, regardless of the value of the DN bit.

[24] FZ

Flush-to-zero mode control bit:

0

Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.

1

Flush-to-zero mode enabled.

Advanced SIMD arithmetic always uses the Flush-to-zero setting, regardless of the value of the FZ bit.

[23:22]RMode

Rounding Mode control field:

b00

Round to nearest (RN) mode

b01

Round towards plus infinity (RP) mode

b10

Round towards minus infinity (RM) mode

b11

Round towards zero (RZ) mode.

Advanced SIMD arithmetic always uses the Round to nearest setting, regardless of the value of the RMode bits.

[21:20] Stride

Stride control used for backwards compatibility with short vector values.

See the ARM Architecture Reference Manual.

[19]-UNK/SBZP.
[18:16]Len

Vector length, used for backwards compatibility with short vector values.

See the ARM Architecture Reference Manual.

[15:8]-UNK/SBZP.
[7]IDCInput Denormal cumulative exception flag.[a]
[6:5]-UNK/SBZP.
[4]IXCInexact cumulative exception flag.[a]
[3]UFCUnderflow cumulative exception flag.[a]
[2]OFCOverflow cumulative exception flag.[a]
[1]DZCDivision by Zero cumulative exception flag.[a]
[0]IOCInvalid Operation cumulative exception flag.[a]

[a] The exception flags, bit [7] and bits [4:0] of the FPSCR are exported on the DEFLAGS output so they can be monitored externally to the processor, if required.


You can access the FPSCR Register with the following VMSR instructions:

VMRS <Rd>, FPSCR ; Read Floating-Point Status and Control RegisterVMSR FPSCR, <Rt> ; Write Floating-Point Status and Control Register
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