1.1. About the FPU

The FPU is a VFPv3-D16 implementation of the ARMv7 floating-point architecture. It provides low-cost, high performance floating-point computation. The FPU supports all addressing modes and operations described in the ARM Architecture Reference Manual.

The FPU features are:

The FPU fully supports single-precision and double-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between floating-point data formats and ARM integer word format, with special operations to perform the conversion in round-towards-zero mode for high-level language support.

The Cortex-A9 FPU provides an optimized solution in performance, power, and area for embedded applications and high performance for general-purpose applications.

The use of VFP vector mode is deprecated in ARMv7. Vector operations are not supported in hardware. If you use vectors, support code is required. See the ARM Architecture Reference Manual for more information.

Note

This manual describes only specific implementation issues. See the ARM Architecture Reference Manual for information on the VFPv3 architecture including the instruction set.

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