2.4.2. Accessing the FPU registers

Access to the FPU registers is controlled by two system control coprocessor registers of the Cortex-A9 processor, accessed through CP15:

See the Cortex-A9 Technical Reference Manual for information on these registers.

To use the FPU in Secure state only

To use the FPU in Secure state only, you must define the CPACR and Floating-Point Exception Register (FPEXC) registers to enable the FPU:

  1. Set the CPACR for access to CP10 and CP11 (the FPU coprocessors):

    LDR r0, =(0xF << 20)MCR p15, 0, r0, c1, c0, 2
    
  2. Set the FPEXC EN bit to enable the FPU:

    MOV r3, #0x40000000 
    VMSR FPEXC, r3
    

To use the FPU in Secure state and Non-secure state

To use the FPU in Secure state and Non-secure state, you must first define the NSACR and then define the CPACR and FPEXC registers to enable the FPU.

  1. Set bits [11:10] of the NSACR for access to CP10 and CP11 from both Secure and Non-secure states:

    MRC p15, 0, r0, c1, c1, 2
    ORR r0, r0, #2_11<<10 ; enable fpu/neonMCR p15, 0, r0, c1, c1, 2
    
  2. Set the CPACR for access to CP10 and CP11:

    LDR r0, =(0xF << 20)MCR p15, 0, r0, c1, c0, 2
    
  3. Set the FPEXC EN bit to enable the FPU:

    MOV r3, #0x40000000 VMSR FPEXC, r3
    
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