3.4.2. VFP instruction timing

Table 3.2 shows the VFP instruction timing.

Table 3.2. VFP instruction timing

NameFormatCyclesSourceResultWriteback

VADD

VSUB

.F Sd,Sn,Sm

.D Dd,Dn,Dm

1-,1,144
VCVT

.F Sd,Sn

.D Dd,Sn

1-,144
VMUL.F Sd,Sn,Sm1-,1,155
VNMUL.D Dd,Dn,Dm2-,1,166

VMLA[a]

.F Sd,Sn,Sm1-,1,188

VMLS

VNMLS

VNMLA

.D Dd,Dn,Dm2-,1,199

VABS

VNEG

.F Sd,Sn

.D Dd,Dn

1-,112
VMOVRt,Sn1-,1--
Rt,Rt2,Dn1-,-,1--
Dd,Rt,Rt21-,1,112
Sd,RtSd,SnDd,Dn1-,112

.F Sd,#imm

.D Dd,#imm

1-,-12
VMRSRt,FPSCR1-,1--
VDIV.F Sd,Sn,Sm10-,1,11515
.D Dd,Dn,Dm20-,1,12525
VSQRT.F Sd,Sn,Sm13-,1,11717
.D Dd,Dn,Dm28-,1,13232
VCMP

.F Sn,Sm

.D Dn,Dm

11,114

[a] If a multiply-accumulate follows a multiply or another multiply-accumulate, and depends on the result of that first instruction, then if the dependency between both instructions are of the same type and size, the processor uses a special multiplier accumulator forwarding. This special forwarding means the multiply instructions can issue back-to-back because the result of the first instruction in cycle 5 is forwarded to the accumulator of the second instruction in cycle 4. If the size and type of the instructions do not match, then Dd or Qd is required in cycle 3. This applies to combinations of the multiply-accumulate instructions VMLA, VMLS, VQDMLA, and VQDMLS, and the multiply instructions VMUL andVQDMUL.


Copyright © 2008-2010 ARM. All rights reserved.ARM DDI 0409F
Non-ConfidentialID050110