Cortex-A9 NEON Media Processing Engine Technical Reference Manual: 2.7.3. Floating-Point Exception Register

The FPEXC Register characteristics are:

Purpose

Provides global enable control of the Advanced SIMD and VFP extensions.

Usage constraints

Only accessible in the Non-secure state if the CP10 and CP11 bits in the NSACR are set to 1, see Non-secure Access Control Register.
Only accessible in privileged modes, and only if access to coprocessors CP10 and CP11 is enabled in the Coprocessor Access Control Register, see Coprocessor Access Control Register.

Configurations

Available in all NEON MPE configurations.

Attributes

See the register summary in Table 2.7.

Figure 2.5 shows the FPEXC Register bit assignments.

Figure 2.5. FPEXC Register bit assignments

Table 2.11 shows the FPEXC Register bit assignments.

Table 2.11. FPEXC Register bit assignments

Bits	Name	Function
[31]	EX	Exception bit: This bit reads-as-zero and ignores-writes. The Cortex-A9 NEON MPE never requires asynchronous exception handling.
[30]	EN	Enable bit: b0 = the Advanced SIMD and VFP extensions are disabled b1 = the Advanced SIMD and VFP extensions are enabled and operate normally. The EN bit is cleared to 0 at reset.
[29]	DEX	Defined synchronous instruction exceptional flag: b0 = no exception has occurred b1 = attempt to perform a VFP vector operation has been trapped^[a]. The DEX bit is cleared to 0 at reset.
[28:26]	-	RAZ/WI.
[25:0]	-	UNK/SBZP.
^[a]The Cortex-A9 NEON MPE hardware does not support the deprecated VFP short vector feature. Attempts to execute VFP data-processing instructions when the FPSCR.LEN field is non-zero result in the FPCSR.DEX bit being set and a synchronous Undefined instruction exception being taken. You can use software to emulate the short vector feature, if required.

You can access the FPEXC Register with the following VMSR instructions:

VMRS <Rd>, FPEXC ; Read Floating-Point Status and Control Register

VMSR FPEXC, <Rt> ; Write Floating-Point Status and Control Register

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