2.2.3. Dynamically configurable VFP register bank size

The dynamically configurable VFP register bank size provides additional support for both VFPv3-D16 and VFPv3-D32 mixed multiprocessor clusters. Cortex-A9 NEON MPE implements thirty-two 64-bit double-precision registers. VFP-only implementations are only required to support sixteen double-precision registers. This register bank disable control enables emulation of a 16-entry double-precision register file, providing both enhanced compatibility and more flexible task scheduling.

Additional control is provided in the Non-Secure Access Control Register. See Non-secure Access Control Register and Coprocessor Access Control Register.

Copyright © 2008-2010 ARM. All rights reserved.ARM DDI 0409F