2.5.2. Non-secure Access Control Register

The NSACR Register defines the Non-secure access rights for the Cortex-A9 NEON MPE and other system functionality.

The NSACR Register is:

Figure 2.2 shows the bit assignments of the NSACR Register relevant to the Cortex-A9 MPE. See the Cortex-A9 Technical Reference Manual for details of other fields in this register.

Figure 2.2. NSACR Register bit assignments


Table 2.5 shows the NSACR Register bit assignments.

Table 2.5. NSACR Register bit assignments

Bits

Field

Function

[31:16]

-

See the Cortex-A9 Technical Reference Manual.
[15]NSASEDIS

Disable Non-secure Advanced SIMD extension functionality:

b0 = Full access provided to CPACR.ASEDIS.

b1 = The CPACR.ASEDIS bit when executing in Non-secure state has a fixed value of 1 and writes to it are ignored.

[14]NSD32DIS

Disable Non-secure use of D16-D31 of the VFP register file:

b0 = Full access provided to CPACR.D32DIS.

b1 = The CPACR.D32DIS bit when executing in Non-secure state has a fixed value of 1 and writes to it are ignored.

[13:12]-See the Cortex-A9 Technical Reference Manual.
[11]CP11

Permission to access coprocessor 11:

b0 = Secure access only. This is the reset value.

b1 = Secure or Non-secure access.

[10]CP10

Permission to access coprocessor 10:

b0 = Secure access only. This is the reset value.

b1 = Secure or Non-secure access.

[9:0]-See the Cortex-A9 Technical Reference Manual.

To access the NSACR Register, read or write CP15 with:

MRC p15, 0,<Rd>, c1, c1, 2 ; Read Non-secure Access Control Register data
MCR p15, 0,<Rd>, c1, c1, 2 ; Write Non-secure Access Control Register data

Table 2.6 shows the results of attempted access for each mode.

Table 2.6. Results of access to the NSACR Register

Secure privilegedNon-secure privilegedUser 
ReadWriteReadWriteReadWrite
DataDataDataUndefined Instruction exceptionUndefined Instruction exceptionUndefined Instruction exception

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