2.5.1. Coprocessor Access Control Register

The CPACR Register sets access rights for the coprocessors CP10 and CP11, that enable the Cortex-A9 NEON MPE functionality. This register also enables software to determine if a particular coprocessor exists in the system.

The CPACR Register is:

Figure 2.1 shows the CPACR Register bit assignments.

Figure 2.1. CPACR Register bit assignments


Table 2.3 shows the CPACR Register bit assignments.

Table 2.3. Coprocessor Access Control Register bit assignments

BitsFieldFunction
[31]ASEDIS

Disable Advanced SIMD extension functionality:

b1 = Disables all instruction encodings identified in the ARM Architecture Reference Manual as being part of the Advanced SIMD extensions but that are not VFPv3 instructions.

b0 = No instructions are disabled.

[30]D32DIS

Disable use of D16-D31 of the VFP register file:

b1 = Disables all instruction encodings identified in the ARM Architecture Reference Manual as being VFPv3 instructions if they access any of registers D16-D31.

b0 = No instructions are disabled.

[29:24]-See the Cortex-A9 Technical Reference Manual.
[23:22]CP11

Defines access permissions for the coprocessor. Access denied is the reset condition and is the behavior for nonexistent coprocessors.

b00 = Access denied. Attempted access generates an Undefined Instruction exception.

b01 = Privileged mode access only.

b10 = Reserved.

b11 = Privileged and User mode access.

[21:20]CP10

Defines access permissions for the coprocessor. Access denied is the reset condition and is the behavior for nonexistent coprocessors.

b00 = Access denied. Attempted access generates an Undefined Instruction exception.

b01 = Privileged mode access only.

b10 = Reserved.

b11 = Privileged and User mode access.

[19:0]-See the Cortex-A9 Technical Reference Manual.

Access to coprocessors in the Non-secure state depends on the permissions set in the Non-secure Access Control Register.

Attempts to read or write the CPACR Register access bits depend on the corresponding bit for each coprocessor in Non-secure Access Control Register. Table 2.4 shows the results of attempted access to coprocessor access bits for each mode.

Table 2.4. Results of access to the CRACR Register

NSACR[11:10]Secure privilegedNon-secure privilegedSecure or Non-secure User
b00R/WRAZ/WIAccess prohibited[a]
b01R/WR/WAccess prohibited[a]

[a] User privilege access generates an Undefined Instruction exception.


To access the CPACR Register, read or write CP15 with:

MRC p15, 0,<Rd>, c1, c0, 2 ; Read Coprocessor Access Control Register
MCR p15, 0,<Rd>, c1, c0, 2 ; Write Coprocessor Access Control Register

When the CPACR is updated, the change to the register is guaranteed to be visible only after the next Instruction Synchronization Barrier (ISB) instruction. When this register is updated, software must ensure that no instruction that depends on the new or old register values is issued before the ISB instruction.

Normally, software uses a read, modify, write sequence to update the CPACR, to avoid unwanted changes to the access settings for other coprocessors.

Note

You must enable CP10 and CP11 in the CPACR Register before accessing any Advanced SIMD or VFP system registers.

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