2.1.2. Enabling Advanced SIMD and floating-point support

From reset, both the Advanced SIMD and VFP extensions are disabled. Any attempt to execute either a NEON or VFP instruction results in an Undefined Instruction exception being taken. To enable software to access Advanced SIMD and VFP features ensure that:

In addition, software must set the FPEXC.EN bit to 1 to enable most Advanced SIMD and VFP operations. See Floating-Point Exception Register.

When Advanced SIMD and VFP operation is disabled because FPEXC.EN is 0, all Advanced SIMD and VFP instructions are treated as undefined instructions except for execution of the following in privileged modes:

Example 2.1 shows how to enable the Advanced SIMD and VFP in ARM Unified Assembly Language (UAL). This code must be executed in privileged mode.

Example 2.1. Enabling Advanced SIMD and VFP

MRC  p15,0,r0,c1,c0,2 ; Read CPACR into r0
ORR  r0,r0,#(3<<20)   ; OR in User and Privileged access for CP10
ORR  r0,r0,#(3<<22)   ; OR in User and Privileged access for CP11
BIC  r0, r0, #(3<<30) ; Clear ASEDIS/D32DIS if set
MCR  p15,0,r0,c1,c0,2 ; Store new access permissions into CPACR
ISB                   ; Ensure side-effect of CPACR is visible
MOV  r0,#(1<<30)      ; Create value with FPEXC (bit 30) set in r0
VMSR FPEXC,r0         ; Enable VFP and SIMD extensions

At this point the Cortex-A9 processor can execute Advanced SIMD and VFP instructions.


Operation is Unpredictable if you configure the Coprocessor Access Control Register (CPACR) such that CP10 and CP11 do not have identical access permissions.

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