3.4.1. Instruction timing tables

The tables in this section provide useful timing information for each category of instruction. The definition of each column is as follows:


Instruction mnemonics are in the ARM UAL format. For legacy mnemonic equivalents, see the ARM Architecture Reference Manual.


This is the register format of the instruction for the timing information that is provided. Where multiple formats are given in a single row, the timing information applies to all those formats. In some cases, the table provides operand type information when different operands require different computation time. For example, Table 3.2, the VFP timing table, contains.F and .D UAL modifiers for single and double-precision operations respectively. Where data-type specifiers are omitted, then you can assume the information applies to all specifiers relevant to the particular entry.


This is the number of issue cycles the particular instruction consumes, and is the absolute minimum number of cycles per instruction if no operand interlocks are present.


The Source field indicates the execution cycle where the source operands must be available if the instruction is to be allowed to issue. The comma separated list matches that of the Format field, indicating the register that each value applies to.

Where two lines are provided for a single format containing quad (Q) registers, this indicates that the source registers are handled independently between top and bottom half double (D) registers. The first line provides the information for the lower half of the quad register and the second line provides the same information for the upper half of the quad register.


The Result field indicates the execution cycle when the result of the operation is ready. At this point, the result might be ready as source operands for consumption by other instructions using forwarding paths. However, some pairs of instructions might have to wait until the value is written back to the register file.


The Writeback field indicates the execution cycle that the result is committed to the register file. From this cycle, the result of the instruction is available to all other instructions as a source operand.


An instruction might not issue if its writeback to a particular register might occur before that of an earlier instruction to the same register.

This section contains the following:

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