3.4.3. VFP load and store instruction timing

Table 3.3 shows the VFP load/store instruction timing.

The SP registers column gives the number of single-precision registers that are operated on. For load and store multiple operations, the number of registers in the list is equal to either 2p or 2p+1 for an even or odd number of registers respectively. Load and stores operations using addresses that are not 64-bit aligned can incur an additional cycle.

Table 3.3. VFP load and store instruction timing

Name Format 64-bit aligned SP registersCyclesSource[a] ResultWriteback
VLDR.F Sd,[]-11-11
VLDR.D Dd,[]Yes21-11
No22-1,21,2
VLDM.F Rn,{...}Yes2pp-1, 2, …, p1, 2, …, p
 2p+1p+1-1, 2, …, p+11, 2, …, p+1
No2pp+1-1, 2, …, p+11, 2, …, p+1
 2p+1p+1-1, 2, …, p+11, 2, …, p+1
VLDM.D Rn,{...}Yes2pp-1, 2, …, p1, 2, …, p
No2pp+1-1, 2, …, p+11, 2, …, p+1
VSTR.F Sd,[]-11---
VSTR.D Dd,[]Yes21---
No22---
VSTM.F Rn,{...}Yes2pp---
 2p+1p+1---
No2pp+1---
 2p+1p+1---
VSTM.D Rn,{...}Yes2pp---
No2pp+1---

[a] Store instructions can be issued before their operands are calculated.


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