Cortex-A9 NEON Media Processing Engine Technical Reference Manual: 3.3. Cortex-A9 NEON MPE instructions

3.3. Cortex-A9 NEON MPE instructions

Table 3.1 shows the instructions supported by the Cortex-A9 NEON MPE, and the instruction set that they are in, either Advanced SIMD or VFP. The data types that each instruction supports are as follows:

D: Double precision floating-point values
F: Single precision floating-point values
H: Half precision floating-point values
I: Integer values
P: Polynomials with single-bit coefficients
X: Operation is independent of data representation.

See the ARM Architecture Reference Manual for details of instruction encodings and functionality.

Table 3.1. Cortex-A9 MPE instructions

Name	Advanced SIMD	VFP	Description
`VABA`	I	-	Absolute Difference and Accumulate
`VABAL`	I	-	Absolute Difference and Accumulate Long
`VABD`	I, F	-	Absolute Difference
`VABDL`	I	-	Absolute Difference Long
`VABS`	I, F	F, D	Absolute
`VACGE`	F	-	Absolute Compare Greater Than or Equal
`VACGT`	F	-	Absolute Compare Greater Than
`VACLE`	F	-	Absolute Compare Less Than or Equal
`VACLT`	F	-	Absolute Compare Less Than
`VADD`	I, F	F, D	Add
`VADDHN`	I	-	Add and Narrow Returning High Half
`VADDL`	I	-	Add Long
`VADDW`	I	-	Add Wide
`VAND`	X	-	Bitwise AND
`VBIC`	I	-	Bitwise Clear
`VBIF`	X	-	Bitwise Insert if False
`VBIT`	X	-	Bitwise Insert if True
`VBSL`	X	-	Bitwise Select
`VCEQ`	I, F	-	Compare Equal
`VCGE`	I, F	-	Compare Greater Than or Equal
`VCLE`	I, F	-	Compare Less Than or Equal
`VCLS`	I	-	Count Leading Sign Bits
`VCLT`	I, F	-	Compare Less Than
`VCLZ`	I	-	Count Leading Zeros
`VCMP`	-	F, D	Compare Setting Flags
`VCNT`	I	-	Count Number of Set Bits
`VCVT`	I, F, H	I, F, D, H	Convert Between Floating-Point and 32-bit Integer Types
`VDIV`	-	F, D	Divide
`VDUP`	X	-	Duplicate
`VEOR`	X	-	Bitwise Exclusive OR
`VEXT`	I	-	Extract Elements and Concatenate
`VHADD`	I	-	Halving Add
`VHSUB`	I	-	Halving Subtract
`VLD1`	X	-	Load Single-Element Structures
`VLD2`	X	-	Load Two-Element Structures
`VLD3`	X	-	Load Three-Element Structures
`VLD4`	X	-	Load Four-Element Structures
`VLDM`	X	F, D	Load Multiple Registers
`VLDR`	X	F, D	Load Single Register
`VMAX`	I, F	-	Maximum
`VMIN`	I, F	-	Minimum
`VMLA`	I, F	F, D	Multiply Accumulate
`VMLS`	I, F	F, D	Multiply Subtract
`VMLAL`	I	-	Multiply Accumulate Long
`VMLSL`	I	-	Multiply Subtract Long
`VMOV`	X	F, D	Move Register or Immediate
`VMOVL`	I	-	Move Long
`VMOVN`	I	-	Move and Narrow
`VMRS`	X	F, D	Move Advanced SIMD or VFP Register to ARM Compute Engine
`VMSR`	X	F, D	Move ARM Core Register to Advanced SIMD or VFP
`VMUL`	I, F, P	F, D	Multiply
`VMULL`	I, F, P	-	Multiply Long
`VMVN`	X	-	Bitwise NOT
`VNEG`	I, F	F, D	Negate
`VNMLA`	-	F, D	Negative Multiply Accumulate
`VNMLS`	-	F, D	Negative Multiply Subtract
`VNMUL`	-	F, D	Negative Multiply
`VORN`	X	-	Bitwise OR NOT
`VORR`	X	-	Bitwise OR
`VPADAL`	I	-	Pairwise Add and Accumulate Long
`VPADD`	I, F	-	Pairwise Add
`VPADDL`	I	-	Pairwise Add Long
`VPMAX`	I, F	-	Pairwise Maximum
`VPMIN`	I, F	-	Pairwise Minimum
`VPOP`	X	F, D	Pop from Stack
`VPUSH`	X	F, D	Push to Stack
`VQABS`	I	-	Saturating Absolute
`VQADD`	I	-	Saturating Add
`VQDMLAL`	I	-	Saturating Double Multiply Accumulate Long
`VQDMLSL`	I	-	Saturating Double Multiply Subtract Long
`VQDMULH`	I	-	Saturating Doubling Multiply Returning High Half
`VQDMULL`	I	-	Saturating Doubling Multiply Long
`VQMOVN`	I	-	Saturating Move and Narrow
`VQMOVUN`	I	-	Saturating Move and Unsigned Narrow
`VQNEG`	I	-	Saturating Negate
`VQRDMULH`	I	-	Saturating Rounding Doubling Multiply Returning High Half
`VQRSHL`	I	-	Saturating Rounding Shift Left
`VQRSHRN`	I	-	Saturating Rounding Shift Right Narrow
`VQRSHRUN`	I	-	Saturating Rounding Shift Right Unsigned Narrow
`VQSHL`	I	-	Saturating Shift Left
`VQSHLU`	I	-	Saturating Shift Left Unsigned
`VQSHRN`	I	-	Saturating Shift Right Narrow
`VQSHRUN`	I	-	Saturating Shift Right Unsigned Narrow
`VQSUB`	I	-	Saturating Subtract
`VRADDHN`	I	-	Rounding Add and Narrow Returning High Half
`VRECPE`	I, F	-	Reciprocal Estimate
`VRECPS`	F	-	Reciprocal Step
`VREV16`	X	-	Reverse in Halfwords
`VREV32`	X	-	Reverse in Words
`VREV64`	X	-	Reverse in Doublewords
`VRHADD`	I	-	Rounding Halving Add
`VRSHL`	I	-	Rounding Shift Left
`VRSHR`	I	-	Rounding Shift Right
`VRSHRN`	I	-	Rounding Shift Right Narrow
`VRSQRTE`	I, F	-	Reciprocal Square Root Estimate
`VRSQRTS`	F	-	Reciprocal Square Root Step
`VRSRA`	I	-	Rounding Shift Right and Accumulate
`VRSUBHN`	I	-	Rounding Subtract and Narrow Returning High Half
`VSHL`	I	-	Shift Left
`VSHLL`	I	-	Shift Left Long
`VSHR`	I	-	Shift Right
`VSHRN`	I	-	Shift Right Narrow
`VSLI`	X	-	Shift Left and Insert
`VSQRT`	-	F, D	Square Root
`VSRA`	I	-	Shift Right and Accumulate
`VSRI`	X	-	Shift Right and Insert
`VST1`	X	-	Store single-element structures
`VST2`	X	-	Store two-element structures
`VST3`	X	-	Store three-element structures
`VST4`	X	-	Store four-element structures
`VSTM`	X	F, D	Store Multiple Registers
`VSTR`	X	F, D	Store Register
`VSUB`	I, F	F, D	Subtract
`VSUBHN`	I	-	Subtract and Narrow
`VSUBL`	I	-	Subtract Long
`VSUBW`	I	-	Subtract Wide
`VSWP`	I	-	Swap Contents
`VTBL`	X	-	Table Lookup
`VTBX`	X	-	Table Extension
`VTRN`	X	-	Transpose
`VTST`	I	-	Test Bits
`VUZP`	X	-	Unzip
`VZIP`	X	-	Zip

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