Cortex-A9 NEON Media Processing Engine Technical Reference Manual: 1.1. About the Cortex-A9 NEON MPE

1.1. About the Cortex-A9 NEON MPE

The Cortex-A9 NEON MPE extends the Cortex-A9 functionality to provide support for the ARM v7 Advanced SIMD and Vector Floating-Point v3 (VFPv3) instruction sets. The Cortex-A9 NEON MPE supports all addressing modes and data-processing operations described in the ARM Architecture Reference Manual.

The Cortex-A9 NEON MPE features are:

SIMD and scalar single-precision floating-point computation
scalar double-precision floating-point computation
SIMD and scalar half-precision floating-point conversion
8, 16, 32, and 64-bit signed and unsigned integer SIMD computation
8 or 16-bit polynomial computation for single-bit coefficients
structured data load capabilities
dual issue with Cortex-A9 processor ARM or Thumb instructions
independent pipelines for VFPv3 and Advanced SIMD instructions
large, shared register file, addressable as:
- thirty-two 32-bit S (single) registers
- thirty-two 64-bit D (double) registers
- sixteen 128-bit Q (quad) registers.
See the ARM Architecture Reference Manual for details of the information that the MPE can hold in the different register formats.

The Cortex-A9 NEON MPE provides high-performance SIMD vector operations for:

unsigned and signed integers
single bit coefficient polynomials
single-precision floating-point values.

The operations include:

addition and subtraction
multiplication with optional accumulation
maximum or minimum value driven lane selection operations
inverse square-root approximation
comprehensive data-structure load instructions, including register-bank-resident table lookup.

See the ARM Architecture Reference Manual for details of the Advanced SIMD instructions.

Note

The Advanced SIMD architecture extension, its associated implementations, and supporting software, are commonly referred to as NEON™ technology.

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