Decodes the AHB address lines to create selects for the peripherals in the debug system.

Combines the debug slave responses for all debug blocks.

The AHB Matrix arbitrates between the processor and debug accesses to the internal PPB and the AHB-Lite external interface.

See Chapter 10 External and Memory Interfaces for more information.

The processor contains the AHB-Access Port (AHB-AP).

The AHB-AP converts the output from an external DP component to an AHB-lite master interface. The AHB-AP master is the highest priority master in the AHB matrix.

The Cortex-M1 system supports 3 possible, configuration selectable, external DP implementations:

See Chapter 8 Debug and Chapter 9 Debug Access Port for more information.

The debug TCM interface comprises one debug interface to access both ITCM and DTCM. Only one TCM can be accessed at any one time.

If your FPGA supports dual ported memory, you can connect both the debug memory interface and core memory interfaces to TCM without any multiplexing. In this case, debug access and core access to TCM is simultaneous. No logic is in place to guarantee predictable results when there are simultaneous accesses on the core and debug interfaces to the same word of memory. If your FPGA memory cannot handle this case predictably, you must either add your own logic or ensure that debug accesses never conflict with core accesses. For example, a debugger can safely access TCMs when the processor is halted or the system reset signal, SYSRESETn, is asserted.

If your FPGA does not support dual ported memory, you must add arbitration logic to connect to both the debug memory interfaces and core memory interfaces.

See Chapter 8 Debug for more information.

The BPU has:

You can individually configure the instruction address comparators to perform a hardware breakpoint. Each comparator can match the address of the instruction being fetched. If there is a match, the BPU ensures that the processor triggers a breakpoint if the instruction that caused the match is executed. Breakpoints are only supported in the code region of the memory map.

See Chapter 8 Debug for more information.

The DW unit has:

You can configure the comparators individually to match either an instruction address or a data address. Masking support for address matching is also supported.

Watchpoints are semi-precise. This means the processor does not halt on the instruction that generates the match, it permits the next instruction to be executed before halting.

See Chapter 8 Debug for more information.

A debugger can access the debug control registers through the PPB to halt and step the processor. The debugger can also access processor registers when the processor is halted.

See Chapter 8 Debug for more information.

The ROM table enables standard debug tools to recognize the processor and the debug peripherals available, and to find the addresses required to access those peripherals.

See Chapter 8 Debug for more information.