Cortex™-M1 Technical Reference Manual 4.5. Pre-emption

4.5. Pre-emption

This section describes the behavior of the processor when it takes an exception.

When the processor takes an exception, it automatically pushes the following eight registers to the stack:

xPSR
ReturnAddress( )
Link Register (LR)
R12
R3
R2
R1
R0.

For information on how ReturnAddress() relates to instruction address, see the ARMv6-M Architecture Reference Manual.

The SP is decremented by eight words on the completion of the stack push. Figure 4.1 shows the contents of the stack after an exception pre-empts the current program flow.

Figure 4.1. Stack contents after a pre-emption

Note

Figure 4.1 shows the order on the stack.
Doubleword alignment of the stack pointer is enforced when stacking commences. Bit [2] of the stack pointer is saved as bit [9] of the stacked xPSR.

After returning from the exception, the processor automatically pops the eight registers from the stack. The exception return value, EXC_RETURN, is automatically loaded into the LR on exception entry to enable exception handlers to be written as normal C/C++ functions without the requirement for a veneer. See the ARMv6-M Architecture Reference Manual for more information.

Table 4.3 describes the steps that the processor takes before it enters an exception.

Table 4.3. Exception entry steps

Action	Description
Push eight registers	Pushes xPSR, ReturnAddress(), LR, R12, R3,R2, R1, and R0 on selected stack.
Read vector table	Reads vector from the appropriate vector table entry: (`0x0`) + (exception_number *4). The vector table read is done after all eight registers are pushed on to the stack.
Read SP_main from vector table	On Reset only, SP_main is updated from the first entry in the vector table. Other exceptions do not modify SP_main in this manner.
Update LR	The LR is set to the appropriate EXC_RETURN to enable correct return from the exception. EXC_RETURN is one of 16 values as defined in ARMv6-M Architecture Reference Manual.
Update PC	Updates PC with the read data from the vector table. No other late-arriving exceptions can be processed until the first instruction of the exception starts to execute.
Load pipeline	Pipeline is filled with sequential instructions at the vector address.

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