Cortex™-M1 Technical Reference Manual 6.2.8. Application Interrupt and Reset Control Register

Use the Application Interrupt and Reset Control Register to:

The register address, access type, and reset value are:

Address

0xE000ED0C.

Access

Access type depends on the individual bit. For more information see Table 6.9.

Reset value

0xFA050000 is the reset value for little-endian.

0xFA058000 is the reset value for BE-8 big-endian.

Figure 6.8 shows the bit assignments of the Application Interrupt and Reset Control Register.

Figure 6.8. Application Interrupt and Reset Control Register bit assignments

Table 6.9 lists the bit assignments of the Application Interrupt and Reset Control Register.

Table 6.9. Application Interrupt and Reset Control Register bit assignments

Bits	Field	Type	Function
[31:16]	VECTKEY	WO	Register key. To write to other parts of this register, you must ensure `0x5FA` is written into the VECTKEY field.
[15]	ENDIANNESS	RO	Data endianness bit. The read value depends on the endian configuration implemented: 0 = little-endian 1 = BE-8 big-endian.
[14:3]	-	-	Reserved.
[2]	SYSRESETREQ	WO	Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.
[1]	VECTCLRACTIVE	WO	Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing can only be set by the DAP when the processor is halted. When this bit is set: clears all active exception status of the processor forces a return to Thread mode forces an IPSR of 0. A debugger must re-initialize the stack.
[0]	-	-	Reserved.

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