Cortex ™-M1 TechnicalReference Manual

Revision: r1p0

Table of Contents

About this manual
Product revision status
Intended audience
Using this manual
Additional reading
Feedback on the processor
Feedback on this manual
1. Introduction
1.1. About the processor
1.2. Components, hierarchy, and implementation
1.2.1. Core
1.2.2. Core memory interface
1.2.3. NVIC
1.2.4. Bus master
1.2.5. AHB-PPB
1.2.6. Debug
1.3. Configurable options
1.4. About the architecture
1.5. Binary compatibility with Cortex-M3processor
1.6. Product revisions
2. Programmer’s Model
2.1. About the programmer’s model
2.1.1. Privilege
2.1.2. Operating modes
2.1.3. Operating states
2.1.4. Main stack and process stack access
2.2. Registers
2.2.1. General-purpose registers
2.2.2. Special-purpose program status registers (xPSR)
2.2.3. Special-Purpose Priority Mask Register
2.2.4. Special-Purpose Control Register
2.3. Data types
2.4. Memory formats
2.5. Instruction set
3. Memory Map
3.1. About the memory map
4. Exceptions
4.1. About the exception model
4.2. Exception types
4.3. Exception priority
4.3.1. Priority levels
4.4. Stacks
4.5. Pre-emption
4.6. Exception exit
4.6.1. Returning the processor from an exception
4.7. Late-arrival
4.8. Exception control transfer
4.9. Activation levels
4.10. Lock-up
5. Clocks and Resets
5.1. About clocks and resets
6. System Control
6.1. About system control
6.2. System control register descriptions
6.2.1. Auxiliary Control Register
6.2.2. SysTick Control and Status Register
6.2.3. SysTick Reload Value Register
6.2.4. SysTick Current Value Register
6.2.5. SysTick Calibration Value Register
6.2.6. CPU ID Base Register
6.2.7. Interrupt Control State Register
6.2.8. Application Interrupt and Reset ControlRegister
6.2.9. Configuration and Control Register
6.2.10. System handler priority registers
6.2.11. System Handler Control and State Register
7. Nested Vectored Interrupt Controller
7.1. About the NVIC
7.2. NVIC programmer’s model
7.2.1. NVIC register map
7.2.2. NVIC register descriptions
7.3. Level versus pulse interrupts
7.4. Resampling level interrupts
7.5. Interrupts as general purpose input
8. Debug
8.1. About debug
8.2. Debug control
8.2.1. Debug Fault Status Register
8.2.2. Debug Halting Control and Status Register
8.2.3. Debug Core Register Selector Register
8.2.4. Debug Core Register Data Register
8.2.5. Debug Exception and Monitor ControlRegister
8.3. ROM table
8.4. BPU
8.4.1. Breakpoint Control Register
8.4.2. Breakpoint Comparator Registers
8.5. DW unit
8.5.1. DW Control Register
8.5.2. DW Program Counter Sample Register
8.5.3. DW Comparator Registers
8.5.4. DW Mask Registers
8.5.5. DW Function Registers
8.6. Debug TCM interface
8.7. Examples of debug register halt, access,and step
8.7.1. Debug halt example
8.7.2. Debug read register access example
8.7.3. Debug write register access example
8.7.4. Debug step example
8.7.5. Breakpoint debug entry example
8.7.6. Exiting core debug
8.8. Data address watchpoint matching
8.9. Semiprecise watchpoints
9. Debug Access Port
9.1. About the DAP
9.2. Debug access
9.2.1. Debug access during core reset
9.2.2. Debug access while core running
9.2.3. Debug access to TCMs
9.3. AHB-AP
9.3.1. AHB-Lite master ports
9.3.2. AHB-AP programmer’s model
9.3.3. AHB-AP clocks and resets
9.3.4. Supported AHB protocol features
9.3.5. Packed transfers
10. External and Memory Interfaces
10.1. About bus interfaces
10.2. External interface
10.3. Write buffer
10.4. Memory attributes
10.5. Memory interfaces
A. Signal Descriptions
A.1. Clocks and Resets
A.2. Miscellaneous
A.3. Interrupt interface
A.4. External AHB-Lite interface
A.5. Memory interfaces
A.6. AHB-AP interface

List of Figures

1. Key to timing diagram conventions
1.1. Processor with debug block diagram
1.2. Processor block diagram
2.1. Processor register set
2.2. Application Program Status Registerbit assignments
2.3. Interrupt Program Status Register bit assignments
2.4. Execution Program Status Registerbit assignments
2.5. Special-purpose Priority Mask Registerbit assignments
2.6. Special-Purpose Control Registerbit assignments
3.1. Processor memory map
4.1. Stack contents after a pre-emption
5.1. Reset signals
6.1. Auxiliary Control Register
6.2. SysTick Control and Status Registerbit assignments
6.3. SysTick Reload Value Register bitassignments
6.4. SysTick Current Value Register bitassignments
6.5. SysTick Calibration Value Registerbit assignments
6.6. CPUID Base Register bit assignments
6.7. Interrupt Control State Registerbit assignments
6.8. Application Interrupt and Reset ControlRegister bit assignments
6.9. Configuration and Control Registerbit assignments
6.10. System Handler Priority Register2 bit assignments
6.11. System Handler Priority Register3 bit assignments
6.12. System Handler Control and StateRegister bit assignments
7.1. Interrupt Priority Registers 0-7bit assignments
8.1. Debug Fault Status Register bit assignments
8.2. Debug Halting Control and StatusRegister bit assignments
8.3. Debug Core Register Selector Registerbit assignments
8.4. Debug Exception and Monitor ControlRegister bit assignments
8.5. Breakpoint Control Register bit assignments
8.6. Breakpoint Comparator Registers bitassignments
8.7. DW Control Register bit assignments
8.8. DW Mask Registers 0-1 format
8.9. DW Function Registers bit assignments
9.1. DAP configuration
9.2. AHB access port internal structure.
9.3. AHB-AP Control/Status Word Registerbit assignments
9.4. AHB-AP Identification Register bitassignments
10.1. ITCM write signal timings
10.2. ITCM read signal timings

List of Tables

1.1. Parameter configurable options
1.2. Pin value configurable options
2.1. Application Program Status Register bit functions
2.2. Interrupt Program Status Register bit assignments
2.3. EPSR bit assignments
2.4. Special-Purpose Priority Mask Register bit assignments
2.5. Special-Purpose Control Register bit assignments
2.6. Required mapping for an AHB-Lite interface
3.1. Processor memory regions
4.1. Exception types
4.2. Exception scenarios
4.3. Exception entry steps
4.4. Exception exit steps
4.5. Exception return behavior
4.6. Transferring to exception processing
4.7. Stack activation levels
4.8. Exception transitions
4.9. Exception subtype transitions
6.1. System control registers
6.2. Auxiliary Control Register bit assignments
6.3. SysTick Control and Status Register bit assignments
6.4. SysTick Reload Value Register bit assignments
6.5. SysTick Current Value Register bit assignments
6.6. SysTick Calibration Value Register bit assignments
6.7. CPUID Base Register bit assignments
6.8. Interrupt Control State Register bit assignments
6.9. Application Interrupt and Reset Control Register bit assignments
6.10. Configuration and Control Register bit assignments
6.11. System Handler Priority Register 2 bit assignments
6.12. System Handler Priority Register 3 bit assignments
6.13. System Handler Control and State Register bit assignments
7.1. NVIC registers
7.2. Interrupt Set-Enable Register bit assignments
7.3. Interrupt Clear-Enable Register bit assignments
7.4. Interrupt Set-Pending Register bit assignments
7.5. Interrupt Clear-Pending Registers bit assignments
7.6. Interrupt Priority Registers 0-31 bit assignments
8.1. Core debug registers summary
8.2. BPU register summary
8.3. DW register summary
8.4. Debug Fault Status Register bit assignments
8.5. Debug Halting Control and Status Register
8.6. Debug Core Register Selector Register
8.7. Debug Exception and Monitor Control Register
8.8. ROM memory
8.9. Breakpoint Control Register bit assignments
8.10. Breakpoint Comparator Registers bit assignments
8.11. DW Control Register bit assignments
8.12. Control Register bit assignments
8.13. DW Comparator Registers bit assignments
8.14. DW Mask Registers bit assignments
8.15. DW Function Registers bit assignments
8.16. Settings for DW Function Registers
9.1. Other AHB-AP ports
9.2. AHB access port registers
9.3. AHB-AP Control/Status Word Register bit assignments
9.4. AHB-AP Transfer Address Register bit assignments
9.5. AHB-AP Data Read/Write Register bit assignments
9.6. Banked Data Register bit assignments
9.7. ROM Address Register bit assignments
9.8. AHB-AP Identification Register bit assignments
10.1. HPROT[3:0] encoding
10.2. Byte-write size
10.3. Instruction and Data TCM sizes
A.1. Reset signals
A.2. Miscellaneous signals
A.3. Interrupt interface
A.4. External AHB-Lite interface
A.5. ITCM interface
A.6. DTCM interface
A.7. Debug ITCM interface
A.8. Debug DTCM interface
A.9. AHB-AP interface

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The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM Limited in goodfaith. However, all warranties implied or expressed, including butnot limited to implied warranties of merchantability, or fitnessfor purpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

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This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 23March 2007 First release of r0p0
Revision B 28September 2007 First release of r0p1
Revision C 20February 2008 Release of Non-Confidential TRM
Revision D 07 May2008 First release of r1p0
Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D