A.1. MBIST controller interface signals

Table A.1 shows the MBIST controller interface signals in a nonparity configuration.

Table A.1. MBIST controller interface signals in a nonparity configuration

SignalTypeDescription
MBISTOUTDATA[255:0]Input

MBIST data out, from Cortex-A9 processor.

MBISTADDR[10:0]Output

MBIST address

MBISTARRAY[19:0]Output

MBIST RAM one-hot chip enables. See Table A.3.

MBISTINDATA[63:0]Output

MBIST data in, to Cortex-A9 processor

MBISTBE[25:0]OutputMBIST write enable.
MBISTWRITEENOutputGlobal write enable.

Table A.2 shows the MBIST controller interface signals in a configuration with parity.

Table A.2. MBIST controller interface signals in a configuration with parity

SignalTypeDescription
MBISTOUTDATA[287:0]Input

MBIST data out, from Cortex-A9 processor.

MBISTADDR[10:0]Output

MBIST address.

MBISTARRAY[19:0]Output

MBIST RAM one-hot chip enables. See Table A.3.

MBISTINDATA[71:0]Output

MBIST data in, to Cortex-A9 processor.

MBISTBE[32:0]OutputMBIST write enable.
MBISTWRITEENOutputGlobal write enable.

Table A.3 shows the MBISTARRAY one-hot chip enables.

Table A.3. MBISTARRAY one-hot chip enables

MBISTARRAY bitRAM name
0BTAC RAM control array 0 and target array 0
1BTAC RAM control array 1 and target array 1
2Instruction tag RAM arrays 0 and 1
3Instruction tag RAM arrays 2 and 3
4Instruction data RAM way 0 (blocks 0 and 1)
5Instruction data RAM way 1 (blocks 2 and 3)
6Instruction data RAM way 2 (blocks 4 and 5)
7Instruction data RAM way 3 (blocks 6 and 7)
8Global History Buffer
9TLB RAM array 0
10TLB RAM array 1
11Data tag RAM arrays 0 and 1
12Data tag RAM arrays 2 and 3
13Data data RAM way 0 (blocks 0 and 4)
14Data data RAM way 1 (blocks 1 and 5)
15Data data RAM way 2 (blocks 2 and 6)
16Data data RAM way 3 (blocks 3 and 7)
17Douter RAM
18SCU tag RAM arrays 0 and 1
19SCU tag RAM arrays 2 and 3

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