3.2.7. ArrayEnables field, MBIR[23:4]

Table 3.9 shows how each bit in the ArrayEnables field selects the cache RAM array to be tested. You can select only one array at a time. Selecting multiple arrays produces unpredictable behavior.

Table 3.9. ArrayEnables field encoding

ArrayEnables MBIR[23:4]RAM name
b00000000000000000001BTAC RAM control array 0 and target array 0
b00000000000000000010BTAC RAM control array 1 and target array 1
b00000000000000000100Instruction tag RAM arrays 0 and 1
b00000000000000001000Instruction tag RAM arrays 2and 3
b00000000000000010000Instruction data RAM way 0 (block 0 and 1)
b00000000000000100000Instruction data RAM way 1 (block 2 and 3)
b00000000000001000000Instruction data RAM way 2 (block 4 and 5)
b00000000000010000000Instruction data RAM way 3 (block 6 and 7)
b00000000000100000000Global History Buffer
b00000000001000000000TLB RAM array 0
b00000000010000000000TLB RAM array 1
b00000000100000000000Data tag RAM arrays 0 and 1
b00000001000000000000Data tag RAM arrays 2and 3
b00000010000000000000Data data RAM way 0 (block 0 and 4)
b00000100000000000000Data data RAM way 1 (block 1and 5)
b00001000000000000000Data data RAM way 2 (block 2 and 6)
b00010000000000000000Data data RAM way 3 (block 3 and 7)
b00100000000000000000Douter RAM
b01000000000000000000SCU tag RAM arrays 0 and 1
b10000000000000000000SCU tag RAM arrays 2 and 3

Copyright © 2008-2011 ARM. All rights reserved.ARM DDI 0414G
Non-ConfidentialID072711