3.1. About the MBIST instruction register

The MBIST executes loaded instructions stored in the MBIST Instruction Register (MBIR). The MBIR is 58 bits wide and divided into a control unit part of 18 bits and a dispatch unit part of 40 bits.

The MBIR is loaded through serial port MBISTDATAIN of the control unit when MBISTSHIFT is asserted. When MBISTSHIFT is asserted again, the control unit passes MBISTDATAIN serially to the dispatch unit through its MBISTTX[3] port.

Figure 3.1 shows the control unit part of the MBIR.

Figure 3.1. MBIST instruction register control unit

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The control unit contains the following fields:

Pattern

Specifies the test algorithm.

Control

Specifies MBIST mode of operation and sticky or nonsticky fail flag.

Write latency

Specifies the number of cycles to enable a RAM write.

Read latency

Specifies the number of cycles to enable a RAM read.

Figure 3.2 shows the dispatch unit part of the MBIR.

Figure 3.2. MBIST instruction register dispatch unit

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The dispatch unit contains the following fields:

CPU On

Controls the data comparison for the CPUs under test.

MaxXAddr

Specifies the number of bits in the X-address counter.

MaxYAddr

Specifies the number of bits in the Y-address counter.

DataWord

Data seed to be used during test. These 4 bits are replicated 16 times to form 64 bits of data.

ArrayEnables

Specifies the RAM under test.

ColumnWidth

Specifies 4, 8, 16, or 32 columns per block of RAM.

CacheSize

Specifies a cache size of 16KB, 32KB, or 64KB.

Field descriptions describes the MBIR fields in more detail.

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