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Figure 1.2 shows the nonparity configuration of the MBIST controller interface to the Automated Test Equipment (ATE) and to the MBIST interface of the Cortex-A9 processor.
Table 1.2 shows the with parity configuration of the MBIST controller interface to the Automated Test Equipment (ATE) and to the MBIST interface of the Cortex-A9 processor.
Figure 1.4 shows the traditional method of accessing RAMs for MBIST.
Because this method significantly reduces the maximum operating frequency, it is not suitable for high-performance designs. Instead, the MBIST controller uses an additional input to the existing functional multiplexors without reducing maximum operating frequency.
Figure 1.5 shows the six pipeline stages used to access the RAM arrays.
The MBIST controller accesses memory through the MBIST interface of the Cortex-A9 processor. Table 1.1 shows the Cortex-A9 processor MBIST interface signals for a configuration without parity.
Table 1.1. Cortex-A9 processor MBIST interface signals nonparity configuration
| Name | Type | Description |
|---|---|---|
| nRESET | Input | Global active LOW reset signal. |
| CLK | Input | Active HIGH clock signal. This clock drives the Cortex-A9 processor logic. |
| MBISTOUTDATA[255:0] | Output | Data out bus from all cache RAM blocks. |
| MBISTENABLE | Input | Select signal for cache RAM array. This signal is the select input to the multiplexors that access the cache RAM arrays for test. When asserted, MBISTENABLE takes priority over all other select inputs to the multiplexors. |
| MBISTARRAY[19:0] | Input | One-hot chip enables to select the RAM arrays for test. |
| MBISTBE[25:0] | Input | Global write enable signal for all RAM arrays. |
| MBISTWRITEEN | Input | Global write enable. |
| MBISTADDR[10:0] | Input | Address signal for cache RAM array. |
| MBISTINDATA[63:0] | Input | Data bus to the RAM arrays. Not all RAM arrays use the full data width. |
Table 1.2 shows the Cortex-A9 processor MBIST interface signals for a configuration with parity.
Table 1.2. Cortex-A9 processor MBIST interface signals with parity configuration
| Name | Type | Description |
|---|---|---|
| nRESET | Input | Global active LOW reset signal. |
| CLK | Input | Active HIGH clock signal. This clock drives the Cortex-A9 processor logic. |
| MBISTOUTDATA[287:0] | Output | Data out bus from all cache RAM blocks. |
| MBISTENABLE | Input | Select signal for cache RAM array. This signal is the select input to the multiplexors that access the cache RAM arrays for test. When asserted, MBISTENABLE takes priority over all other select inputs to the multiplexors. |
| MBISTARRAY[19:0] | Input | One-hot chip enables to select the RAM arrays for test. |
| MBISTBE[32:0] | Input | Global write enable signal for all RAM arrays. |
| MBISTWRITEEN | Input | Global write enable. |
| MBISTADDR[10:0] | Input | Address signal for cache RAM array. |
| MBISTINDATA[71:0] | Input | Data bus to the RAM arrays. Not all RAM arrays use the full data width. |
The interface of the MBIST controller communicates with both the ATE and the MBIST interface of the Cortex-A9 processor. See Appendix A Signal Descriptions for descriptions of the MBIST controller interface signals. See the Cortex-A9 Processor Technical Reference Manual for more information about the MBIST interface.
| Copyright © 2008-2011 ARM. All rights reserved. | ARM DDI 0414G |
| Non-Confidential | ID072711 |
| PDF version | |
| Home > Introduction > MBIST controller interface |