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Figure 3.12 shows the address map that the Distributor provides for the targets_spi_<INTID> Registers.
The ARM Generic Interrupt Controller Architecture Specification describes the behavior of the Interrupt Processor Targets Registers (ICDIPTRn).
In Figure 3.12:
The Distributor does not provide registers for INTIDs < 32. If a processor reads from a location where an SGI or PPI is implemented then the Distributor returns:
0x01Processor read a targets_spi_<INTID> Register for CPU Interface 0.
0x02Processor read a targets_spi_<INTID> Register for CPU Interface 1.
0x04Processor read a targets_spi_<INTID> Register for CPU Interface 2.
0x08Processor read a targets_spi_<INTID> Register for CPU Interface 3.
0x10Processor read a targets_spi_<INTID> Register for CPU Interface 4.
0x20Processor read a targets_spi_<INTID> Register for CPU Interface 5.
0x40Processor read a targets_spi_<INTID> Register for CPU Interface 6.
0x80Processor read a targets_spi_<INTID> Register for CPU Interface 7.
If a processor reads from a location where an SGI or PPI is
not implemented then the Distributor returns 0x00.
You must use the sgi_control Register to program the target CPU Interfaces for SGIs.
If you configure the GIC to support ≤ 987 SPIs then it reduces the number of targets_spi_<INTID> Registers accordingly.
| Copyright © 2008, 2009 ARM Limited. All rights reserved. | ARM DDI 0416B |
| Non-Confidential | |
| PDF version | |
| Home > Programmers Model > Distributor register descriptions > Target Registers (ICDIPTRn) |