PrimeCell Generic Interrupt Controller (PL390) Technical Reference Manual: 3.2.12. PPI Status Register

The ppi_if<n> Register characteristics are:

Purpose: Each bit returns the status of the ppi_c<n>[15:0] inputs for CPU Interface <n>.
Usage constraints: Only accessible to processors in Secure state.
Configurations: This register is only available when the GIC is configured to provide two or more CPU Interfaces.
Note
If the GIC is configured to provide a single CPU Interface then the Distributor returns 0x00000000.
Attributes: See the register summary in Table 3.1.

Figure 3.14 shows the ppi_if<n> Register bit assignments.

Figure 3.14. ppi_if<n> Register bit assignments

Table 3.4 shows the ppi_if<n> Register bit assignments.

Table 3.4. ppi_if<n> Register bit assignments

Bits	Name	Function
[31:16]	-	Reserved
[15:0]	ppi_status	Returns the status of the ppi_c<n>[15:0] inputs on the Distributor: Bit [`X`] = 0 ppi_c<n>[x] is LOW Bit [`X`] = 1 ppi_c<n>[x] is HIGH. Note These bits return the actual status of the ppi_c<n>[15:0] signals. The Pending Set Registers (ICDISPRn) and Pending Clear Registers (ICDICPRn) also provide the ppi_c<n>[15:0] status but because you can write to these registers then they might not contain the actual status of the ppi_c<n>[15:0] signals.

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