PrimeCell® Generic Interrupt Controller (PL390) Technical Reference Manual

Revision: r0p0

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1. Introduction
1.1. About the GIC
1.2. Compliance
1.3. Features
1.4. Interfaces
1.5. Configurable options
1.6. Test features
1.7. Product documentation, design flow, and architecture
1.7.1. Documentation
1.7.2. Design flow
1.7.3. ARM architecture and protocol information
1.8. Product revisions
2. Functional Overview
2.1. Functional interfaces
2.1.1. AMBA slave interfaces
2.1.2. Distributor
2.1.3. CPU Interface
2.1.4. Clock and reset
2.1.5. enable and match signals
2.2. Implementation-defined behavior
2.2.1. Number of CPU Interfaces
2.2.2. Number of interrupt inputs
2.2.3. Legacy interrupts
2.2.4. Programmable trigger-mode of PPIs
2.2.5. Lockable SPI (LSPI) support
2.2.6. Number of priority levels
2.2.7. Effect of updating the Priority Level Register for Active interrupts
2.2.8. Interrupt prioritization of interrupts with equal priority
2.2.9. Arbitration of SPIs which target multiple processors
2.2.10. Initial value of the Interrupt Security Register
2.2.11. Access restrictions of registers that are specific to a CPU Interface
2.2.12. Minimum supported value in the Binary Point Register
3. Programmers Model
3.1. About the programmers model
3.1.1. Distributor register map
3.1.2. CPU Interface register map
3.2. Distributor register descriptions
3.2.1. Interrupt Controller Type Register (ICDICTR)
3.2.2. Distributor Implementer Identification Register (ICDIIDR)
3.2.3. Interrupt Security Registers (ICDISRn)
3.2.4. Enable Set Registers (ICDISERn)
3.2.5. Enable Clear Registers (ICDICERn)
3.2.6. Pending Set Registers (ICDISPRn)
3.2.7. Pending Clear Registers (ICDICPRn)
3.2.8. Active Status Registers (ICDABRn)
3.2.9. Priority Level Registers (ICDIPRn)
3.2.10. Target Registers (ICDIPTRn)
3.2.11. Interrupt Configuration Registers (ICDICRn)
3.2.12. PPI Status Register
3.2.13. SPI Status Registers
3.2.14. Peripheral Identification Registers
3.2.15. PrimeCell Identification Registers
3.3. CPU Interface register descriptions
3.3.1. CPU Interface Control Register (ICCICR)
3.3.2. CPU Interface Implementer Identification Register (ICCIIDR)
3.3.3. Peripheral Identification Registers
3.3.4. PrimeCell Identification Registers
3.4. Additional programming information
3.4.1. Software initialization process for GICs that support a single security state
3.4.2. Software initialization process for GICs that support the Security Extensions
3.4.3. Risk of Denial of Service (DoS) when the GIC supports the Security Extensions
4. Programmers Model for Test
4.1. About the programmers model for test
4.2. Distributor integration test registers
4.2.1. Legacy Interrupt Registers
4.2.2. Match Register
4.2.3. Enable Register
4.3. CPU Interface integration test registers
4.3.1. Integration Test Enable Register
4.3.2. Interrupt Output Register
4.3.3. Match Register
4.3.4. Enable Register
A. Signal Descriptions
A.1. Clock and reset signals
A.2. AXI slave interface signals
A.2.1. Write address (AXI-AW) channel signals
A.2.2. Write data (AXI-W) channel signals
A.2.3. Write response (AXI-B) channel signals
A.2.4. Read address (AXI-AR) channel signals
A.2.5. Read data (AXI-R) channel signals
A.3. AHB-Lite signals
A.3.1. AHB-Lite slave interface for the Distributor
A.3.2. AHB-Lite slave interface for the CPU Interface
A.4. Interrupt signals
A.5. Miscellaneous signals
A.5.1. cfgsdisable
A.5.2. Enable and match
B. Interrupt Signaling
B.1. Signaling interrupts when the GIC supports a single security state
B.2. Signaling interrupts when the GIC supports the Security Extensions
C. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. Interfaces on the GIC
1.2. Example multiprocessor system
1.3. Example uniprocessor system
2.1. GIC block diagram
2.2. AXI slave interface
2.3. AHB-Lite slave interface
2.4. Distributor
2.5. Interrupt manipulation logic
2.6. CPU Interface
3.1. Distributor register map
3.2. CPU Interface register map
3.3. ic_type Register bit assignments
3.4. dist_ident Register bit assignments
3.5. Interrupt Security Register address map
3.6. Enable Set Register address map
3.7. Enable Clear Register address map
3.8. Pending Set Register address map
3.9. Pending Clear Register address map
3.10. Active Status Register address map
3.11. Priority Level Register address map
3.12. targets_spi_<INTID> Register address map
3.13. spi_config Register address map
3.14. ppi_if<n> Register bit assignments
3.15. spi Register bit assignments
3.16. spi Register address map
3.17. periph_id_[3:0] Register bit assignments
3.18. periph_id_[7:4] Register bit assignments
3.19. periph_id_8 Register bit assignments
3.20. PrimeCell ID Register bit assignments
3.21. cpu_if_ident Register bit assignments
3.22. Initialization process for GICs that support a single security state
3.23. Initialization process for GICs that support the Security Extensions, sheet 1 of 2
3.24. Initialization process for GICs that support the Security Extensions, sheet 2 of 2
4.1. legacy_int<n> Register bit assignments
4.2. match_d<n> Register bit assignments
4.3. enable_d<n> Register bit assignments in the Distributor
4.4. integ_en_c<n> Register bit assignments
4.5. interrupt_out<n> Register bit assignments
4.6. match_c<n> Register bit assignments in a CPU Interface
4.7. enable_c<n> Register bit assignments in a CPU Interface
B.1. Interrupt signaling using nirq_c
B.2. Interrupt signaling using nirq_c and nfiq_c

List of Tables

2.1. Attribute formats
3.1. Distributor register summary
3.2. ic_type Register bit assignments
3.3. dist_ident Register bit assignments
3.4. ppi_if<n> Register bit assignments
3.5. spi Register bit assignments
3.6. periph_id_[3:0] Register bit assignments
3.7. periph_id_0 Register bit assignments
3.8. periph_id_1 Register bit assignments
3.9. periph_id_2 Register bit assignments
3.10. periph_id_3 Register bit assignments
3.11. periph_id_[7:4] Register bit assignments
3.12. periph_id_4 Register bit assignments
3.13. periph_id_5 Register bit assignments
3.14. periph_id_6 Register bit assignments
3.15. periph_id_7 Register bit assignments
3.16. periph_id_8 Register bit assignments
3.17. component_id Register bit assignments
3.18. CPU Interface register summary
3.19. cpu_if_ident Register bit assignments
4.1. Distributor test register summary
4.2. legacy_int<n> Register bit assignments
4.3. match_d<n> Register bit assignments
4.4. enable_d<n> Register bit assignments in the Distributor
4.5. CPU Interface test register summary
4.6. integ_en_c<n> Register bit assignments
4.7. interrupt_out<n> Register bit assignments
4.8. match_c<n> Register bit assignments in a CPU Interface
4.9. enable_c<n> Register bit assignments in a CPU Interface
A.1. Clock and reset signals
A.2. AXI-AW signals for the Distributor
A.3. AXI-AW signals for a CPU Interface
A.4. AXI-W signals for the Distributor
A.5. AXI-W signals for a CPU Interface
A.6. AXI-B signals for the Distributor
A.7. AXI-B signals for a CPU Interface
A.8. AXI-AR signals for the Distributor
A.9. AXI-AR signals for a CPU Interface
A.10. AXI-R signals for the Distributor
A.11. AXI-R signals for a CPU Interface
A.12. AHB-Lite slave interface signals for the Distributor
A.13. AHB-Lite slave interface signals for the CPU Interface
A.14. Interrupt signals
A.15. cfgsdisable signal
A.16. enable_d<n> and match_d<n> signals
A.17. enable_c<n> and match_c<n> signals
C.1. Differences between issue A and issue B

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The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

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Confidentiality Status

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A28 April 2008First release for r0p0
Revision B23 November 2009Second release for r0p0
Copyright © 2008, 2009 ARM Limited. All rights reserved.ARM DDI 0416B