PrimeCell ® µDMAController (PL230) Technical Reference Manual

Revision:r0p0


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Further reading
Feedback
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the µDMAC
1.1.1. Features of the controller
1.2. Terminology
2. Functional Overview
2.1. Functional description
2.1.1. APB block
2.1.2. AHB block
2.1.3. DMA control block
2.1.4. Example system configuration
2.2. Functional operation
2.2.1. APB slave interface
2.2.2. AHB master interface
2.2.3. DMA control
2.2.4. Channel control data structure
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Register descriptions
3.2.1. DMA status
3.2.2. DMA configuration
3.2.3. Channel control database pointer
3.2.4. Channel alternatecontrol data base pointer
3.2.5. Channel wait on requeststatus
3.2.6. Channel software request
3.2.7. Channel useburst set
3.2.8. Channel useburst clear
3.2.9. Channel request maskset
3.2.10. Channel request mask clear
3.2.11. Channel enable set
3.2.12. Channel enable clear
3.2.13. Channel primary-alternate set
3.2.14. Channel primary-alternateclear
3.2.15. Channel priority set
3.2.16. Channel priority clear
3.2.17. Bus error clear
3.2.18. Peripheral Identification Registers
3.2.19. PrimeCell identification Registers
4. Programmer’s Model for Test
4.1. Register descriptions
4.1.1. Integration configuration
4.1.2. DMA stall status
4.1.3. DMA request status
4.1.4. DMA single requeststatus
4.1.5. DMA done set
4.1.6. DMA done clear
4.1.7. DMA active set
4.1.8. DMA active clear
4.1.9. Bus error set
A. Signal Descriptions
A.1. Clock and reset signals
A.2. AHB-Lite master interface signals
A.2.1. Signals tied to a steady state
A.3. APB interface signals
A.4. DMA control signals
A.5. Interrupt signal
Glossary

List of Figures

1. Key to timing diagram conventions
2.1. Block diagram
2.2. APB slave interface
2.3. AHB-Lite master interface
2.4. DMA control
2.5. Example system
2.6. DMA signaling when peripherals usepulse requests
2.7. DMA signaling when peripherals uselevel requests
2.8. dma_done signaling
2.9. DMA signaling when peripherals use dma_waitonreq
2.10. DMA signaling when peripherals use dma_waitonreq and dma_sreq
2.11. Polling flowchart
2.12. Ping-pong example
2.13. Memory scatter-gather example
2.14. Peripheral scatter-gather example
2.15. Memory map for 32 channels, includingthe alternate data structure
2.16. Memory map for three DMA channels,including the alternate data structure
2.17. channel_cfg bit assignments
3.1. dma_status Register bit assignments
3.2. dma_cfg Register bit assignments
3.3. ctrl_base_ptr Register bit assignments
3.4. alt_ctrl_base_ptr Register bit assignments
3.5. dma_waitonreq_status Register bitassignments
3.6. chnl_sw_request Register bit assignments
3.7. chnl_useburst_set Register bit assignments
3.8. chnl_useburst_clr Register bit assignments
3.9. chnl_req_mask_set Register bit assignments
3.10. chnl_req_mask_clr Register bit assignments
3.11. chnl_enable_set Register bit assignments
3.12. chnl_enable_clr Register bit assignments
3.13. chnl_pri_alt_set Register bit assignments
3.14. chnl_pri_alt_clr Register bit assignments
3.15. chnl_priority_set Register bit assignments
3.16. chnl_priority_clr Register bit assignments
3.17. err_clr Register bit assignments
3.18. periph_id_[3:0] Register bit assignments
3.19. periph_id_0 Register bit assignments
3.20. periph_id_1 Register bit assignments
3.21. periph_id_2 Register bit assignments
3.22. periph_id_3 Register bit assignments
3.23. periph_id_4 Register bit assignments
3.24. pcell_id_[3:0] Register bit assignments
3.25. pcell_id_0 Register bit assignments
3.26. pcell_id_1 Register bit assignments
3.27. pcell_id_2 Register bit assignments
3.28. pcell_id_3 Register bit assignments
4.1. integration_cfg Register bit assignments
4.2. dma_stall_status Register bit assignments
4.3. dma_req_status Register bit assignments
4.4. dma_sreq_status Register bit assignments
4.5. dma_done_set Register bit assignments
4.6. dma_done_clr Register bit assignments
4.7. dma_active_set Register bit assignments
4.8. dma_active_clr Register bit assignments
4.9. err_set Register bit assignments

List of Tables

2.1. HTRANS signaling
2.2. HSIZE signaling
2.3. Protection signaling
2.4. Address increments
2.5. Rules when channels and enabled and requests are not masked
2.6. Rules for disabled channels
2.7. AHB bus transfer arbitration interval
2.8. DMA channel priority
2.9. DMA cycle types
2.10. channel_cfg for a primary data structure, in memory scatter-gathermode
2.11. channel_cfg for a primary data structure, in peripheral scatter-gathermode
2.12. Address bit settings for the channel control data structure
2.13. Permitted base addresses
2.14. src_data_end_ptr bit assignments
2.15. dst_data_end_ptr bit assignments
2.16. channel_cfg bit assignments
2.17. DMA cycle of six words using a word increment
2.18. DMA cycle of 12 bytes using a halfword increment
3.1. Register summary
3.2. dma_status Register bit assignments
3.3. dma_cfg Register bit assignments
3.4. ctrl_base_ptr Register bit assignments
3.5. alt_ctrl_base_ptr Register bit assignments
3.6. dma_waitonreq_status Register bit assignments
3.7. chnl_sw_request Register bit assignments
3.8. chnl_useburst_set Register bit assignments
3.9. chnl_useburst_clr Register bit assignments
3.10. chnl_req_mask_set Register bit assignments
3.11. chnl_req_mask_clr Register bit assignments
3.12. chnl_enable_set Register bit assignments
3.13. chnl_enable_clr Register bit assignments
3.14. chnl_pri_alt_set Register bit assignments
3.15. chnl_pri_alt_clr Register bit assignments
3.16. chnl_priority_set Register bit assignments
3.17. chnl_priority_clr Register bit assignments
3.18. err_clr Register bit assignments
3.19. periph_id_[3:0] Register bit assignments
3.20. periph_id_0 Register bit assignments
3.21. periph_id_1 Register bit assignments
3.22. periph_id_2 Register bit assignments
3.23. periph_id_3 Register bit assignments
3.24. periph_id_4 Register bit assignments
3.25. pcell_id_[3:0] Register bit assignments
3.26. pcell_id_0 Register bit assignments
3.27. pcell_id_1 Register bit assignments
3.28. pcell_id_2 Register bit assignments
3.29. pcell_id_3 Register bit assignments
4.1. Test register summary
4.2. integration_cfg Register bit assignments
4.3. dma_stall_status Register bit assignments
4.4. dma_req_status Register bit assignments
4.5. dma_sreq_status Register bit assignments
4.6. dma_done_set Register bit assignments
4.7. dma_done_clr Register bit assignments
4.8. dma_active_set Register bit assignments
4.9. dma_active_clr Register bit assignments
4.10. err_set Register bit assignments
A.1. Clock and reset signals
A.2. Steady state signals
A.3. paddr[ ] bus
A.4. pclken signal
A.5. DMA control signals
A.6. Interrupt signal

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This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 19 March2007 First release for r0p0
Copyright © 2007 ARM Limited. All rights reserved. ARM DDI 0417A
Non-Confidential