PrimeCell™ DDR2 Dynamic Memory Controller (PL341) Technical Reference Manual 3.3.4. Memory Configuration Register

3.3.4. Memory Configuration Register

The memory_cfg Register configures the memory controller. It can only be read from and written to in the Config or Low-power state. Figure 3.11 shows the register bit assignments.

Figure 3.11. memory_cfg Register bit assignments

Table 3.5 lists the register bit assignments.

Table 3.5. memory_cfg Register bit assignments

Bits	Name	Function
[31:23]	-	Read undefined, write as zero.
[22:21]	active_chips	Enables the refresh command generation for the number of memory chips. It is only possible to generate commands up to and including the number of chips in the configuration that the memc_status Register defines: 2’b00 = 1 chip 2’b01 = 2 chips 2’b10 = 3 chips 2’b11 = 4 chips.
[20:18]	qos_master_bits	Encodes the four bits of the 8-bit AXI ARID that select one of the 16 QOS values: 3’b000 = ARID[3:0] 3’b001 = ARID[4:1] 3’b010 = ARID[5:2] 3’b011 = ARID[6:3] 3’b100 = ARID[7:4] 3'b101 = ARID[8:5] 3'b110 = ARID[9:6] 3'b111 = ARID[10:7].
[17:15]	memory_burst	Encodes the number of data accesses that are performed to the SDRAM for each Read and Write command: 3’b010 = Burst 4. This value must also be programmed into the SDRAM mode register using the direct_cmd register at offset `0x8`, and must match it.
[14]	-	Reserved. Ignored for writes, read as zero.
[13]	auto_power_down	When this is set, the memory interface automatically places the SDRAM into power-down state by deasserting CKE when the command FIFO has been empty for PowerDownPrd memory clock cycles.
[12:7]	power_down_prd	Number of memory clock cycles for auto power-down of the SDRAM.
[6]	-	Reserved. Ignored for writes, read as zero.
[5:3]	row_bits	Encodes the number of bits of the AXI address that comprise the row address: 3’b000 = 11 bits 3’b001 = 12 bits 3’b010 = 13 bits 3’b011 = 14 bits 3’b100 = 15 bits 3’b101 = 16 bits.
[2:0]	column_bits	Encodes the number of bits of the AXI address that comprise the column address: 3’b000 = Reserved. 3’b001 = 9 bits. 3’b010 = 10 bits. 3’b011 = 11 bits. This means that A0-A9, and A11 are used for column address because A10 is a dedicated AP bit. 3’b100 = Reserved.

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